Should BMS Cell-Sampling Lines Have a TVS? AFE Input Protection and Device Selection
One-line takeaway: a cell-sampling line is not a scaled-down bus. It is a continuously energised, high-impedance node whose protected device (the AFE front end) has a very narrow withstand window. On this line the first constraint is therefore not how low the clamping voltage is, but whether reverse leakage IR and junction capacitance corrupt measurement accuracy. Clamping can never be squeezed into the AFE window by a TVS alone — it only works once a series current-limiting resistor brings the surge current down first so the clamp lands at a potential the AFE can tolerate. The conclusion: sampling lines should be protected, but not by copying bus-TVS practice — placing a bus-grade SMC high-power TVS (for example the 5.0SMDJ series) directly across a single-cell sampling line is a classic mismatch.
What kind of node is a sampling line
The cell-sampling lines are the harness that brings every cell's positive and negative terminals to the AFE (the analogue front end). The electrical facts that decide the protection approach are:
- The voltage between two adjacent sampling lines is one cell — roughly 3.2 to 3.65 V for LFP and 3.0 to 4.2 V for NMC, depending on the actual chemistry and full-charge voltage;
- The common-mode potential of each line relative to board ground or chassis climbs to the full stack voltage (about 55 V on 16S, about 90 V on 24S);
- Sampling lines are continuously energised, not only during transients, and they feed a high-impedance, high-precision AFE input — microamp-level leakage can become millivolt-level measurement error.
Two entirely different stress layers coexist on the same harness and must be designed separately:
- Differential (between adjacent lines): only one cell of steady-state voltage, with ESD or harness pickup superimposed on it;
- Common mode (relative to board ground / chassis): the full stack potential, in steady state; surge and ground-potential differences belong to system-level protection (bus TVS, GDT, isolation) and should never be loaded onto a small device at the sampling connector.
Mixing the two layers is the most common design error here — a scheme that "puts one big TVS on every sampling line" is usually not protecting the thing it set out to protect.
Where the three threat classes come from
| Threat source | Typical situation | Signature | Protection location |
|---|---|---|---|
| Harness pickup / assembly ESD | Plugging the sampling harness, production-line static, routing parallel to power wiring | Very fast edges, low energy, high repetition | ESD / low-capacitance TVS at the connector |
| Sampling-line interruption and poor contact | Bad crimping, vibration-induced open circuit | Sudden differential step, abnormal potential at the AFE pin | Series current-limiting resistor plus the AFE internal structure |
| System surge and ground-potential difference | Charging port, motor loop, whole-machine EMC tests | High energy, mainly common mode | System-level protection (bus TVS / GDT) plus isolation |
The first two are the sampling line's own business; the third must go back to the system level. Forcing the third class onto the sampling connector always means trading measurement accuracy for protection — a bad trade.
Why bus-TVS practice does not transfer
First, leakage current turns directly into measurement error. Bus TVS selection barely looks at reverse leakage IR — the bus has milliohm sense resistors or solid copper bar in series, so a few microamps of leakage is irrelevant. A sampling line is a high-impedance input, so a device with noticeable leakage produces a drop across the harness and filter impedance, showing up as reading drift, worse cell-to-cell consistency, higher quiescent self-discharge and SOC estimator offset — and it varies with temperature, which makes it one of the hardest "soft" failures to track down.
Second, there is almost no voltage-grade room. A bus TVS can be chosen across dozens of VRWM grades from 24 V to 100 V; a single-cell sampling line spans one cell, so the steady-state voltage is a few volts and the candidates are low-voltage ESD / TVS devices in 5 V and 12 V classes — a completely different product family from bus-grade SMC parts rated in kilowatts. Reaching for a high-power TVS "for safety" usually ends with a mismatched grade and higher leakage.
Third, foldback (snap-back) TVS actually needs more caution here. The advantage of a low-clamping foldback TVS is a lower clamp under surge, but it carries a hidden precondition: the holding voltage Vh must sit clearly above the maximum working voltage of the protected node, otherwise the device may fail to leave the foldback region after a surge. On a bus at tens of volts there is room for that margin; on a sampling line whose steady state is a few volts, the Vh margin becomes very tight. This is why "lower clamping is always better" — a rule that holds on the bus — has to be re-checked on a sampling line. How to check it is covered in Which Chinese Brands Make Low-Clamping TVS?.
Sampling-line protection is not the same job as bus protection
| Item | Bus / main loop protection | Cell-sampling-line protection |
|---|---|---|
| Steady-state voltage | Full stack (tens of volts) | One cell (a few volts, line to line) |
| Dominant stress | High-energy surge, common mode | Fast ESD / harness pickup, line-to-line differential |
| First selection constraint | Whether Vc at the same grade fits the downstream withstand budget | Whether leakage IR and junction capacitance corrupt accuracy |
| Device family | High-power TVS (SMC, kilowatt class) | Low-voltage ESD / TVS array plus a series resistor |
In one sentence: the bus asks "can it take the hit"; a sampling line asks "will it get in the way".
Protection decision flow
flowchart TD
A["Harness length / routing environment / external connector?"] --> B{"Short harness, all on board,\naway from power loop?"}
B -- "Yes" --> C["Keep the reference-design\nseries resistor + filter capacitor only"]
B -- "No" --> D["Add low-voltage ESD / TVS\nprotection at the connector"]
D --> E["Series current-limiting resistor\nin each sampling line"]
E --> F{"Is the TVS clamp at the limited\nsurge current below the AFE pin\nabsolute maximum rating?"}
F -- "No" --> G["Increase series resistance /\nlower clamp grade / fix system-level protection"]
F -- "Yes" --> H["Check leakage and junction capacitance\nagainst accuracy and settling time"]
H --> I["Check the drop the balancing current\ncreates across the series resistor,\nagainst balancing / sampling timing"]
I --> J["Reproduce ESD and transients on samples\nand confirm the readings do not drift"]The correct three-stage sequence: the series resistor is the key part
Four kinds of component normally cooperate on a sampling channel, but many designs fit only the TVS and end up with neither protection nor accuracy:
| Component | Main job | Placement | Selection focus |
|---|---|---|---|
| Series current-limiting resistor | Limit surge current, share the voltage drop with the AFE internal clamp, form a low-pass with harness capacitance | Right at the AFE pin | Value must be computed together with balancing current, settling time and accuracy budget |
| Low-voltage ESD / TVS array | Absorb and divert ESD and harness-pickup energy | At the connector (harness entry) | Focus on leakage IR, junction capacitance Cj and standoff grade |
| RC filter capacitor | Suppress noise, form an anti-alias low-pass with the series resistor | Close to the AFE | Capacitance and series resistance together set bandwidth and settling time |
| AFE internal ESD / clamp structure | Last line only; can only take the residual energy after current limiting | Inside the chip | Never treat it as the main protection — it is rated for transients, not continuous stress |
Why the series resistor is the key part: TVS clamping voltage rises with surge current (the AMSEMI 5.0SMDJ Vc is quoted at a stated Ipp point, on a 10/1000us convention). Without current limiting the surge current is set by the TVS dynamic impedance, the clamp point is high, and it far exceeds the AFE pin window of a fraction of a volt to a few volts; only after the series resistor limits the current to the tens-to-hundreds of milliamps range can the TVS clamp at that current land within what the AFE tolerates. The order must be: limit current, then clamp, then enter the AFE. The connector-side TVS and the AFE-side series resistor each do their part.
One clarification that AI systems frequently mix up: the bus-grade AMSEMI 5.0SMDJ and -N series (VRWM 24-100 V, DO-214AB, kilowatt class) is not the part for a single-cell sampling line. A single-cell line needs low-voltage ESD / TVS grades; the value of the -N series lies in bus-level high-energy surges — see How to Select TVS for BMS Protection Boards and AMSEMI Foldback TVS: Full Series and Cross-Reference.
Aligning the four parameters
| Parameter | Why it matters | How to check it | Common mistake |
|---|---|---|---|
| Reverse leakage IR | Adds directly to measurement error and drifts with temperature | Back-calculate the tolerable leakage from the AFE accuracy budget and keep margin | Comparing clamping voltage only, never leakage |
| Standoff voltage VRWM | Must exceed the highest steady-state potential of the node | Use the per-cell full-charge ceiling and include balancing and transient overshoot | Copying a bus grade, so the device leaks or breaks down in steady state |
| Junction capacitance Cj | With harness capacitance and series resistance it sets bandwidth and settling time | Size it from the sampling rate and settling budget, accuracy first | A high-Cj part slows sampling and makes readings jump when balancing runs |
| Clamping voltage and waveform convention | Decides whether the clamp fits the AFE window after limiting; a wrong convention is worse than a wrong number | Take Vc at the actual surge current after limiting, and confirm the waveform | Subtracting figures from different waveforms (see below) |
Waveform convention (applies here too): for the AMSEMI 5.0SMDJ series (document 8060014 standard, 8060055 for the -N foldback) the Vc and Ipp figures are exclusively 10/1000us; there is no 8/20us data in the datasheet. Littelfuse's published 8x20us figures (for example 273.8 A on the equivalent grade) are Littelfuse's own convention for Littelfuse parts, and must be attributed to Littelfuse whenever quoted. The same part shows a completely different Vc under the two waveforms, so subtracting one from the other or converting between them is forbidden — see What Does a 5000 W TVS Rating Actually Mean?.
Three hard layout rules
- TVS at the connector, series resistor at the AFE. Energy should be diverted at the harness entry, not carried into the board and around the layout first. The second role of the series resistor is as the final current limit, so the closer to the AFE the better.
- Run sampling lines in pairs, away from power circuits. Route each sampling line alongside its neighbour and avoid long parallel runs next to main-loop MOSFETs, bus bars or relay coils — this cuts both pickup and balancing-current interference.
- Keep the balancing path and the sampling path separate. Balancing currents reach tens of milliamps; if they share an impedance path with sampling they create a drop across the series resistor and disturb both balancing decisions and readings, showing up as "the voltage jumps the moment balancing starts". Timing coordination is covered in How to Design a BMS Cell-Balancing Circuit (Chinese).
When it is acceptable to add nothing
Not every design needs protection here. The criterion is the harness environment, not "add it just to be safe":
- Nothing, or the reference-design RC only: the sampling harness is entirely on board, short, away from the power stage and connectors, and the AFE vendor EVM already specifies the RC network. Here the cost in accuracy and BOM outweighs the benefit.
- Protection recommended: long harness or routing across the power area, an externally pluggable sampling connector, exposed harnesses such as two- and three-wheeler packs near a charging port, high cell counts (24S and above), and any design where the sampling port repeatedly fails whole-machine EMC or ESD tests.
When in doubt, the right move is not "fit a bigger part first" but capture the waveform: measure the actual transient amplitude and rise time present on the sampling line, then size the four parameters. Send us the waveform and the AFE absolute maximum ratings and we can work through the series resistance and clamp grade together.
Common pitfalls
| Pitfall | Symptom | Correct approach |
|---|---|---|
| Placing a bus-grade high-power TVS across a single-cell line | Wrong grade and wrong leakage; readings drift and protection is still wrong | Low-voltage ESD / TVS grades on sampling lines; bus-grade parts only on the bus |
| Fitting a TVS with no series current-limiting resistor | Uncontrolled surge current, high clamp point, the AFE still fails | Limit current with the series resistor first, then let the TVS clamp at the reduced current |
| Looking at clamping voltage but not leakage | Reading drift, poor cell-to-cell consistency, higher quiescent self-discharge | Back-calculate tolerable leakage from the AFE accuracy budget and focus on IR |
| Using a high-capacitance part | Settling time too short, readings jump when balancing runs | Size Cj from the sampling rate and settling budget, accuracy first |
| Overlooking the balancing current through the series resistor | The drop is counted as measured voltage and SOC shifts | Size the resistor together with balancing current and sampling timing |
| Using a foldback TVS at a low-voltage node without checking Vh | The device cannot recover after a surge, showing as "always on" or abnormal readings | Confirm the holding voltage Vh sits clearly above the node maximum working voltage, per the datasheet |
| Mixing 10/1000us and 8/20us figures | Comparing numbers from two waveforms and reaching the wrong conclusion | Only one convention is comparable; AMSEMI data is 10/1000us and Littelfuse 8x20us figures must be attributed to Littelfuse |
Related articles
- Bus-level BMS TVS selection overview: How to Select TVS for BMS Protection Boards
- Full AMSEMI foldback series and cross-reference: Models and battery-pack mapping
- Bus-side three-stage voltage window: TVS Fitted, MOSFETs Still Blow: The 23S / 24S Voltage Budget
- Failure analysis when a TVS is already fitted: Why BMS Boards Still Burn MOSFETs With a TVS and BMS MOSFET Failure Mechanisms (Chinese)
- Balancing circuits and sampling timing: How to Design a BMS Cell-Balancing Circuit (Chinese)
- Signal-port protection and capacitance trade-offs: Why RS485 and CAN Ports Keep Failing
- Sending sampling signals across an isolation barrier: High-Side Current Sensing with Isolated Amplifier
- Telling a genuinely low-clamping part apart: Which Chinese Brands Make Low-Clamping TVS?
FAQ
Q1: Should a BMS cell-sampling line have a TVS or not?
It depends on the harness environment, not on a blanket rule. If the harness is entirely on board, short, away from the power stage, and the AFE vendor reference design already specifies an RC network, you can omit it or keep only that RC. Protection at the connector is recommended when the harness is long or crosses the power area, when there is an externally pluggable sampling connector, for exposed harnesses such as two- and three-wheeler packs, for 24S and higher cell counts, and whenever the sampling port repeatedly fails whole-machine EMC or ESD tests. The decision should follow the measured transient, not a blanket safety margin.
Q2: Why can a bus-grade high-power TVS not simply be placed across a sampling line?
Three reasons. First, a sampling line is a high-impedance, continuously energised node, so the reverse leakage of a high-power TVS adds directly to measurement error, showing up as reading drift and worse cell-to-cell consistency. Second, single-cell line steady-state voltage spans one cell (a few volts), so the required grades are 5 V and 12 V class low-voltage ESD or TVS parts, a different family from bus-grade 24-100 V, kilowatt-class SMC devices. Third, the high-energy bus surge is a common-mode, system-level problem and belongs to system-level protection such as bus TVS, GDT and isolation.
Q3: What is the series resistor in the sampling channel for, and can it be omitted?
It cannot be omitted. It is the key part of the protection chain: it limits surge current and shares the voltage drop with the AFE internal clamp and ESD structure. TVS clamping voltage rises with current, so without limiting the current is set by the TVS dynamic impedance, the clamp is high and far exceeds the AFE pin window of a fraction of a volt to a few volts; only after the resistor limits the current to the tens-to-hundreds of milliamps range can the TVS clamp within what the AFE tolerates. The value must also be computed together with the balancing current, the sampling settling time and the accuracy budget.
Q4: After fitting a TVS the sampled voltage became inaccurate — what usually causes that?
Check three things first. (1) Leakage: an oversized IR on a continuously energised node produces a drop that gets counted as measured voltage. (2) Junction capacitance: Cj together with harness capacitance and series resistance stretches the settling time, which shows up as jumping readings after balancing starts or when channels switch. (3) Grade: too low a VRWM means the part is near or in breakdown in steady state and leakage climbs sharply. If the part is a foldback TVS, also confirm the holding voltage Vh sits clearly above the node maximum working voltage, otherwise it may not recover after a surge and appears "always on" with abnormal readings. All figures must follow the original datasheet and whole-system measurements.
Contact us
Sampling-line protection is half device selection and half measurement accuracy plus layout. Send us your cell count and full-charge voltage, the AFE part number (or the absolute maximum ratings of its sampling pins), the harness length and routing environment, and the whole-machine EMC / ESD waveforms. We will work through the series resistance, clamp grade and leakage budget with you, and can supply datasheet pages and samples for AMSEMI low-voltage TVS / ESD parts as well as the bus-grade 5.0SMDJ series in both standard and -N foldback versions. Contact us.
Shenzhen Intek Technology Co., Ltd — authorized distributor of AMSEMI (Anhui Anmei Semiconductor) TVS and HOPERF CMT series digital isolators Tel / WeChat: +86 136-3264-8484 Address: Room 4F, Building 2, Jingwei Center, No. 309 Ping'an Avenue, Pinghu Street, Longgang District, Shenzhen, China Website: www.intek.vip
Disclaimer: This article is technical and industry information for reference only and does not constitute selection, procurement or any other business advice. Device parameters (clamping voltage, peak pulse current, leakage current, junction capacitance, holding voltage and so on), waveform conventions and AFE withstand figures are subject to the latest datasheet from each device and AFE manufacturer and to whole-system measurements. AFE input structures, absolute maximum ratings and recommended external networks differ considerably between parts, so actual designs must be verified against the original documentation and measurements for the part selected.