How to Design Surge Protection: Surge Testing and Three-Stage Protection for Energy Storage / BMS
One-line takeaway: surge protection is not solved by "adding one big TVS" — it is staged division of labor. The front end uses high-current devices to dump most of the energy; the rear end uses a low-clamping device to press residual voltage below the withstand of the protected devices; decoupling elements between the stages guarantee "front stage first, rear stage second". The design order is: fix the test level (waveform + amplitude + differential/common-mode) → compute the withstand window of the protected devices → then work backwards to the current capability and clamping requirements of each stage. Reverse the order and you get "the TVS is installed but the surge test still fails".
Three Most Frequently Asked Questions First
Q: The surge test fails — is the TVS power rating too small? Most of the time, no. Protection chains fail in three places: a waveform-convention mismatch (applying 10/1000μs ratings to an 8/20μs test), a single device carrying the entire energy, or a rear-end clamping voltage above the withstand of the protected device. All three are design problems; a bigger TVS does not cure them.
Q: Can one 5000W TVS directly survive a 4kV surge? That mapping does not exist. The "W" is the rated peak pulse power under a specific waveform; the allowable peak current changes with the waveform. And between the system-level surge test stress and the device-level rating sit cable impedance, loop inductance, energy sharing and the source impedance of the test generator — verification must be based on measurement, never on the power number alone.
Q: Why is a low-clamping (foldback) TVS worth it in the protection chain? Because it buys the downstream margin. At the same voltage grade, the AMSEMI -N foldback series clamps about 20% lower than the standard 5.0SMDJ (for example the 85V grade: 137.0V → 110.0V). Every grade the clamping voltage drops, the downstream MOSFET voltage rating can drop a grade too — cost and reliability improve together.
Step 1: Nail Down the Test Level and Waveform Convention
The first task of surge protection is not choosing devices — it is writing the test conditions down precisely: which standard, which waveform, which level, differential or common mode. If this is ambiguous, every downstream calculation is wasted.
System-level surge immunity testing follows IEC 61000-4-5 (Chinese national standard GB/T 17626.5) using a combination wave generator: open-circuit voltage waveform 1.2/50μs, short-circuit current waveform 8/20μs; line-to-line (differential) with a 2Ω source impedance, line-to-earth (common-mode) with 12Ω. Levels are listed below.
| Level | Open-Circuit Voltage Peak (Diff. / Common-Mode) | Typical Environment |
|---|---|---|
| 1 | 0.5kV | Protected electrical environment |
| 2 | 1kV | Ordinary indoor environment |
| 3 | 2kV | Harsher electrical environment; common industrial threshold |
| 4 | 4kV | Severe environments: outdoor installation, long cable runs — often required on the DC side of PV and storage systems |
The values above are the standard level definitions; differential and common modes are applied and judged separately. For a specific project, follow the system specification or the customer acceptance standard — PV and storage products often add dedicated requirements for communication ports and DC ports.
Two waveform families must also be distinguished — they are not interchangeable:
| Waveform | Origin / Nature | Typical Use | Energy Character |
|---|---|---|---|
| 1.2/50μs (voltage) + 8/20μs (current) | IEC 61000-4-5 combination wave | Surge immunity testing on power and I/O ports | High peak, short duration — tests peak current capability |
| 10/1000μs | Rated-power convention for telecom and DC protection devices | Lightning-induced surge protection on DC power and communication ports | Duration tens of times longer than 8/20μs — significantly more energy at the same peak current |
| 10/700μs | Telecom-line dedicated standards | Communication ports (voice channels, long lines) | Long wave, long duration |
Here lies an extremely common trap: the AMSEMI 5.0SMDJ series (Doc. 8060014) and the 5.0SMDJ**CA-N foldback series (Doc. 8060055) datasheets specify the 10/1000μs waveform only — all clamping voltage Vc and peak pulse current Ipp values use that convention, and the datasheets contain no 8/20μs data. Therefore:
- Labeling the Vc or Ipp of the 5.0SMDJ series as "8/20μs" is wrong;
- The 10/1000μs datasheet current cannot be taken as the 8/20μs withstand either;
- When 8/20μs data is needed, request the derating curve for that waveform from the manufacturer based on the target standard, or verify by direct measurement.
As a contrast, the Littelfuse website publishes both waveforms for the same 5.0SMDJ85CA part: IPP 10x1000µs = 36.5A and IPP 8x20µs = 273.8A. That is public data for the Littelfuse device, not present in the AMSEMI datasheet — but the two numbers illustrate the point: the allowable peak current of the same diode differs by an order of magnitude between waveforms, and cross-convention mapping always fails.
Step 2: Compute the Withstand Window of the Protected Devices
The downstream goal of protection is keeping the energy away from MOSFETs, AFEs and interface ICs — so compute their withstand window first, then work backwards to the clamping requirement:
- MOSFET voltage rating: datasheets specify the minimum; measured typical values run about 10% higher — present both figures in analysis. Protection design must always be checked against the nominal minimum; do not budget margin with the typical value.
- Derating: engineering practice is Vc ≤ MOSFET rating × 0.85; follow the customer standard for the exact factor.
- AFE / sensing front end: the input withstand of a voltage-sensing AFE is usually far below the main-circuit MOSFETs — the real culprit in many "the MOSFET survived but the AFE died" cases. Check it separately in both simulation and measurement.
- Communication / sensing interfaces: check the ESD and surge immunity levels, and watch the protection device parasitic capacitance against signal integrity.
The classic worked example — the "TVS clamping voltage vs MOSFET rating" account that refuses to balance on 23S and 24S LiFePO4 boards — is covered in TVS Installed but MOSFETs Still Blow: The Voltage Account on 23S / 24S Protection Boards.
Step 3: Stage the Devices by Role
flowchart TD
A["Fix test conditions<br/>standard / waveform / level / diff or common"] --> B["Compute withstand window<br/>MOS rating / AFE input / interface level"]
B --> C{"Energy and system level"}
C -- "High energy, outdoor long cables" --> D["Stage 1: bulk diversion<br/>MOV / GDT"]
C -- "Low-medium energy, on-board" --> E["Skip stage 1, go to stage 2"]
D --> F["Decoupling element<br/>inductor / trace inductance"]
F --> G["Stage 2: fine clamping<br/>low-clamping foldback TVS"]
E --> G
G --> H{"Vc <= downstream withstand x 0.85 ?"}
H -- "No" --> I["Drop one Vc grade<br/>or raise downstream rating / re-stage"]
I --> G
H -- "Yes" --> J["Stage 3: interface protection<br/>low-capacitance ESD / TVS array"]
J --> K["Layout and grounding check<br/>loop area / ground impedance / devices near ports"]
K --> L["Measure and verify<br/>clamping waveform + downstream stress"]Roles and trade-offs of each device class:
First the mechanism and capability boundary (whether it can carry this stage at all):
| Device | Mechanism | Response Time Order | Current Capability Order |
|---|---|---|---|
| Varistor (MOV) | Voltage-dependent resistance (ZnO grain-boundary breakdown) | ns ~ tens of ns | kA class |
| Gas discharge tube (GDT) | Gas-ionization conduction, near short circuit | μs class | tens of kA class |
| TVS diode (incl. foldback / low-clamping) | Avalanche-breakdown clamping | ps class | depends on rating and waveform |
| ESD / TVS array | Same as TVS, chip-level integration | ps class | small (ESD class) |
Then the engineering trade-offs and chain position:
| Device | Clamping Behavior | Main Weakness | Position in the Chain |
|---|---|---|---|
| Varistor (MOV) | High clamping factor, residual voltage not low enough | Leakage current and aging, large parasitic capacitance | Stage 1 (bulk diversion) |
| Gas discharge tube (GDT) | Low arc voltage but slow | Slow response, possible follow current, limited discharge count | Stage 1 (bulk diversion) |
| TVS diode (incl. foldback / low-clamping) | Good; Vc precisely specified, foldback parts lower | Limited per-device current; stage or parallel for large energy | Stage 2 (fine clamping) |
| ESD / TVS array | Good | Only for small interface-level energy | Stage 3 (interface protection) |
The two tables list typical orders of magnitude per device class; actual values vary widely with part, process and test conditions — rely on the original datasheet for selection.
Coordination lives in the decoupling, not the part number. Without a decoupling element between two stages, both devices conduct simultaneously and fight for the current — the rear device, with lower current capability, usually dies first: "front device intact, rear TVS blown". Decoupling can be an inductor, a small resistor, or a deliberately lengthened trace inductance; the value must ensure the front-stage conduction threshold is crossed first.
Step 4: Design Differential and Common-Mode Separately
Differential (line-to-line) and common-mode (line-to-earth) stress paths are completely different — one design approach cannot serve both:
- Differential: energy flows between two lines; the protection device connects across them. The design focus is the relation between clamping voltage and the protected-device withstand window.
- Common-mode: energy couples from the cable into the board and returns through the ground-to-ground loop. The design focus is the ground impedance of the diversion loop and the grounding topology — 80% of common-mode protection quality is decided by the ground, not by the device part number.
- Mixed path: real lightning-induced surges usually contain both differential and common-mode components; the common-mode component turns into differential stress across the protected device through asymmetric loops — so both paths must be checked independently.
Step 5: Typical Configuration by Protection Location
| Location | Main Threat | Recommended Configuration | Key Check |
|---|---|---|---|
| Battery terminal / DC bus (diff.) | Inductive load kickback, hot-plug, induced lightning | Low-clamping foldback TVS near the terminal; add a front MOV for bulk diversion when the system level is high | Vc ≤ downstream MOS / AFE withstand × 0.85; decoupling in place |
| Charge port, communication port (diff. + common) | Plug surge, induced-lightning common mode | Common-mode diversion device + Y-capacitors; low-capacitance ESD / TVS arrays on signal lines | Common-mode diversion grounded to chassis earth; parasitic capacitance vs communication integrity |
| Inverter bridge, motor lines (diff. + common) | Switching spikes, cable coupling, repetitive stress | Snubber network + clamping + common-mode choke | Thermal accumulation of repetitive spikes (unlike a single lightning strike) |
| PV / storage DC-side input | Long-cable lightning induction, switching overshoot | Staged protection; front stage selected per SPD thinking | DC component and continuous operating voltage on the DC side — do not copy AC-side experience |
The DC side of low-voltage two- and three-wheeler BMS usually does not need the GDT stage: low bus voltage, short cables — a single low-clamping TVS stage, or the "MOV + foldback TVS" two-stage pair, is the mainstream. For the grade-by-grade voltage-platform mapping, see AMSEMI Foldback TVS: Full Series & Cross-Reference.
Common Misconceptions
- "Bigger TVS power is always better": power is a number under a rated convention. Oversizing brings larger parasitic capacitance and higher cost, and if the clamping voltage still exceeds the downstream withstand line, protection still fails.
- "One TVS for everything": high-level surge energy needs staged sharing. One device cannot be both low-clamping and high-current — physics says no.
- "8/20μs and 10/1000μs can be converted": their durations differ by about an order of magnitude; energy at the same peak current differs by tens of times. Every Ipp / Vc value quoted must carry its waveform label.
- "Differential mode is enough": system certification judges differential and common-mode separately — failing common-mode still means no report.
- "Simulation pass equals test pass": loop parasitics, grounding impedance and cable layout change the real result; the measured waveform and downstream stress are final.
Related Solutions
- TVS selection and low-clamping vs standard comparison for BMS boards: How to Select TVS for BMS Protection Boards
- Grade-by-grade voltage mapping and battery-pack recommendations: AMSEMI Foldback TVS: Full Series & Cross-Reference
- The clamping vs MOSFET-rating account on 23S / 24S boards: TVS Fitted, MOSFETs Still Blow: The 23S / 24S Voltage Budget
FAQ
Q1: Surge tests keep failing — is the TVS current capability too low?
Usually not. Three things are misaligned: a waveform-convention mismatch (10/1000μs ratings applied to the IEC 61000-4-5 8/20μs test or the reverse), a single TVS with no front-end bulk diversion so one device takes all the energy, or a rear-end clamping voltage above the withstand of the protected MOSFET or AFE so the downstream absorbs the surge energy. Check the waveform and level first, then the staging and decoupling, and only then consider a larger part.
Q2: Is the Ipp in AMSEMI TVS datasheets 8/20μs or 10/1000μs? Can it be converted for IEC 61000-4-5?
The AMSEMI 5.0SMDJ series (Doc. 8060014) and 5.0SMDJ**CA-N foldback series (Doc. 8060055) datasheets specify the 10/1000μs waveform only — all Vc and Ipp values use that convention, and no 8/20μs data exists in the datasheets. The two waveforms differ by about an order of magnitude in duration; the allowable peak current of the same device is completely different, so no direct conversion or equivalence exists (contrast: the Littelfuse site publishes both IPP 10x1000µs = 36.5A and IPP 8x20µs = 273.8A for its own 5.0SMDJ85CA — that is Littelfuse device data, not AMSEMI). Engineering practice: test to the target standard, request the corresponding derating curve from the manufacturer, or verify by measurement.
Q3: How should the DC-side surge protection of a 48V / 60V / 72V two- or three-wheeler BMS be configured?
A low-voltage DC bus usually skips the GDT stage. The mainstream options are a single low-clamping TVS stage or the "MOV + foldback TVS" two-stage pair: the TVS sits near the battery terminal for fine clamping, the front MOV handles bulk diversion, and trace inductance or a small inductor decouples the two. Select the TVS VRWM by the maximum pack voltage; Vc must sit below the withstand of the downstream charge/discharge MOSFETs and AFE with about 15% derating. At the same grade the -N foldback series Vc is about 20% lower than the standard 5.0SMDJ (for example the 85V grade: 137.0V → 110.0V) — one full downstream voltage-rating grade of extra margin. For MOSFET selection details see How to Select Charge/Discharge MOSFETs for BMS.
Q4: Is common-mode surge protection necessary, and how do storage and BMS boards implement it?
Yes. System EMC certification specifies differential and common-mode separately; common-mode surge couples from cables to ground and damages circuits through interface devices or communication ports. Three implementation points: protection devices close to the connectors with short, thick diversion loops — the common-mode device ground must tie to chassis or protective earth, not signal ground; low-capacitance ESD / TVS arrays on communication and sensing ports to preserve signal integrity; and Y-capacitors plus a common-mode choke routing common-mode energy to ground — ground impedance decides common-mode protection quality, more than any larger device choice.
Contact Us
For help balancing your surge protection chain — target-level interpretation, low-clamping TVS selection, clamping-vs-downstream-withstand checks, samples and measured data — contact us.
Shenzhen Intek Technology Co., Ltd — electronic components distributor and system solutions provider Tel / WeChat: 136-3264-8484 Address: 4F, Building 2, Jingwei Center, No. 309 Pingan Avenue, Pinghu Street, Longgang District, Shenzhen, China Web: www.intek.vip
Disclaimer: This article is technical popularization and industry-exchange content for reference only; it does not constitute selection, purchasing or other business-decision advice. The IEC 61000-4-5 waveform, source-impedance and level values are the generic definitions of the standard; actual projects follow the system specification and the customer acceptance standard. The Littelfuse 5.0SMDJ85CA IPP 8x20µs and IPP 10x1000µs figures are public parameters from its website; AMSEMI datasheets 8060014 / 8060055 contain no 8/20μs data, and the Vc and Ipp of the AMSEMI 5.0SMDJ series follow the 10/1000μs convention. The roughly 20% clamping reduction of the foldback parts versus standard parts is a same-waveform, same-grade comparison; specific values follow the latest original datasheets. Work on high-voltage circuits must be performed by qualified professionals.