How to Isolate an I2C Sensor on the High-Voltage Side? Direction Control, Level Shift and Pull-Up of Isolated I2C
Bottom line: I2C is an open-drain, bidirectional, one-wire-two-direction bus; you cannot just string a one-way digital isolator like UART / SPI. Three engineering paths: use a dedicated isolated I2C device (e.g. HOPERF CMT810X series, bidirectional auto-direction recognition + both-side 1.8 to 5.5V level shift) is easiest; two one-way isolators back-to-back plus discrete circuitry to make a bidirectional channel works but costs more to debug; the optocoupler scheme is inferior in both speed and life. After choosing, close on three steps: isolation position and withstand → level shift → pull-up resistor and speed.
flowchart TD
A["① Clarify the need<br/>who is on high-voltage side / how many slaves / what speed"] --> B{"Need isolation?"}
B -- "Same low-voltage domain<br/>common ground reliable" --> C["No isolation<br/>add ESD or TVS protection if needed"]
B -- "Across high-voltage domain<br/>high-side sampling / meter / isolated inter-board" --> D{"Slave count and topology?"}
D -- "Single MCU to single or few slaves<br/>standard or fast mode mainly" --> E["Scheme 1: dedicated isolated I2C<br/>CMT810X series (first choice)"]
D -- "Existing general-isolator inventory<br/>can accept discrete debug" --> F["Scheme 2: two one-way isolators back-to-back<br/>plus discrete logic for bidirectional"]
D -- "Low speed, migrate old optocoupler design" --> G["Scheme 3: optocoupler plus transistor<br/>speed and life limited"]
E --> H["② Set withstand and package<br/>3.75kVrms / 5kVrms selectable"]
F --> H
G --> H
H --> I["③ Set level shift<br/>both-side VCC 1.8 to 5.5V"]
I --> J["④ Set pull-up and speed<br/>standard 100k / fast 400k / high-speed"]
J --> K["⑤ Verify: waveform / clock stretching / multi-slave arbitration"]First, two most-asked questions
Q: When does I2C need isolation?
I2C itself is an in-board short-distance bus; on the same control board with reliable common ground it does not need isolation. Isolation is needed in these cases: first, the sensor or slave is on the high-voltage side — e.g. bus-voltage sampling AFE, temperature/voltage acquisition chips inside a high-voltage box, separated from the low-voltage MCU by hundreds of volts; second, inter-board / inter-pack communication — between BMS slave boards and sensing boards, between energy-storage system control boards and in-box cards, where ground-potential difference is uncontrolled; third, safety requirement — user-accessible interfaces of smart meters, medical and industrial equipment must be isolated from the internal high-voltage domain. The purpose of isolation is the same as in the general digital-isolator overview: break the ground loop, block common-mode transients, meet withstand and creepage requirements (see Which positions in an energy-storage system actually need isolation? and What does 5kVrms on an isolator mean?).
Q: Why can't a single one-way digital isolator isolate I2C?
Because the I2C SDA (and the SCL extension in fast mode) is a bidirectional open-drain line: master write, slave acknowledge, multi-master arbitration, and slave clock stretching all happen on the same line. UART / SPI are clearly one-way signal flows, so a channel-direction-fixed digital isolator can just sit across; if you make I2C one-way, the slave acknowledge bit (ACK) cannot return to the master, and the bus locks. To use a general isolator you must use two one-way isolators back-to-back plus diode and transistor circuitry to "split the bidirectional line into two directions" — that is the origin of Scheme 2: it works, but component count, loop delay and debug cost all go up. A dedicated isolated I2C device puts this logic inside the chip; the outside is still the standard SCL/SDA two pins.
Step 1: set isolation position and withstand caliber
First draw clearly which side is the "danger domain": place the isolated I2C device on the signal path crossing the boundary, with Side 1 (primary) to the low-voltage MCU side and Side 2 (secondary) to the high-voltage-side sensor. Check withstand on the dual caliber — the datasheet isolation-withstand test value (3.75kVrms / 5kVrms class) is not the long-term working voltage; operating isolation voltage, transient spike and creepage are checked against the system safety requirement separately, and only a wide-body package meets stricter creepage. This caliber is identical to gate-driver and CAN isolation, so we will not expand.
Step 2: comparison of the three isolation schemes
| Scheme | Principle | Advantage | Limitation |
|---|---|---|---|
| Dedicated isolated I2C (e.g. CMT810X) | Direction recognition done inside the chip; outside still standard SCL/SDA | Fewest components, no direction-control pin, both-side level shift, simple debug | Need to select by speed class and withstand class |
| Two one-way isolators back-to-back | Split bidirectional line into two directions, with diode/transistor synthesizing open-drain bus | Can reuse existing general-isolator inventory | Many peripheral discretes, loop delay extends setup time, multi-slave arbitration prone to problems, high debug cost |
| Optocoupler + transistor | Traditional: optocoupler transmits one direction, transistor returns the other | High withstand achievable, smooth legacy-design migration | Low speed (hundreds of kbps class), large periphery, CTR degrades with temperature and aging |
The conclusion is direct: for new designs prioritize a dedicated isolated I2C. Scheme 2 is only worth it when "you have a lot of general-isolator inventory" or "modifying an old board without changing layout"; the optocoupler scheme is used only at low speed or to inherit an old architecture (for the general judgment of optocoupler overall replacement migration see Can an optocoupler be replaced directly by a digital isolator?).
Step 3: how to use a dedicated isolated I2C (CMT810X series)
Using the HOPERF CMT810X series (e.g. CMT8100N) as an example, key capabilities and usage:
| Capability | Description | Selection / usage tip |
|---|---|---|
| SCL/SDA bidirectional auto-direction recognition | No direction-control pin needed; master write and slave ACK switch automatically | Directly replace the isolation segment between "MCU and sensor", zero software change |
| Both-side level shift VCC1/VCC2 both 1.8 to 5.5V | Each side can use its own power domain | Low-side 3.3V MCU to high-side 5V sensor solved by one device for both isolation and level shift |
| Speed class covers standard / fast / high-speed I2C | Covers 100kHz / 400kHz and high-speed mode needs | Set speed by the slave actual capability; do not default to high-speed (see pull-up section) |
| Isolation withstand 3.75kVrms / 5kVrms selectable | Corresponding to narrow-body and wide-body packages | Select by system safety requirement; note test value is not working voltage |
The exact model naming, package, speed ceiling and certification list of CMT810X follow the HOPERF datasheet; this article gives only series-level capability and usage.
Step 4: pull-up resistor and speed — the easiest place for isolated I2C to fail
I2C is an open-drain bus; the pull-up resistor sets the edge speed; an isolated I2C device adds a fixed propagation delay in the loop, making edges slower and timing margin smaller. Engineering order-of-magnitude reference (adjust by bus capacitance and measurement; follow datasheet and measured waveform):
| Speed class | Common pull-up order | Note |
|---|---|---|
| Standard mode 100kHz | about 4.7kΩ | When bus capacitance is small (few loads) a larger value saves power |
| Fast mode 400kHz | about 2.2kΩ | Lower further when capacitance is large; watch sink current vs pin capability |
| High-speed mode | about 1kΩ to start | Steep edge, sensitive to layout and capacitance; first confirm the slave really supports it |
Troubleshooting rule: if speed does not come up, look at the waveform first, then timing. A trailing rising edge means the pull-up is too large or bus capacitance too large (reduce load, shorten traces, lower pull-up); lost ACK and clock-stretching timeouts first confirm the isolator propagation delay is within the timing budget, then check whether the slave is doing clock stretching — some MCU I2C peripherals handle stretching timeout very crudely, showing as "occasional NACK, retrying fixes it".
Common pitfalls and troubleshooting
| Symptom | Common cause | Action |
|---|---|---|
| Lost ACK bit, bus lock | One-way isolator hard-strung into I2C | Switch to dedicated isolated I2C or back-to-back scheme |
| Erratic speed, occasional NACK | clock stretching timeout / propagation delay squeezing timing | Lower speed, check delay budget, check MCU timeout config |
| Trailing rising edge, ramp waveform | Pull-up too large / bus capacitance large / long trace | Lower pull-up, reduce load, shorten isolation-segment trace |
| Bus abnormal when high-side power-up order wrong | Communication before secondary supply ready | Per power-up sequence, supply secondary first (see layout article) |
| Isolation two-side power domains mixed | No level shift done, directly shared VCC | Use device both-side independent supply capability, separate power domains |
| Isolation segment damaged by ESD | No ESD protection on signal port | Put TVS on the bus port (watch junction capacitance effect on I2C edge) |
Related solutions
- Main selection line: How to select digital isolators?
- Isolation position planning: Which positions in an energy-storage system actually need isolation?
- Isolation-withstand dual caliber: What does 5kVrms on an isolator mean?
- Communication-port isolation and protection: How to select isolated CAN and RS-485 transceivers?, RS485 / CAN communication port keeps failing — what to do?
- High-side analog isolation: How to do high-side current sensing?
- Isolation implementation: Isolation done but useless? Isolation barrier PCB layout, creepage and secondary isolated supply, How to make an on-board auxiliary supply?
- MCU and system support: Which MCU for energy-storage BMS? GD32 selection guide, How to design BMS cell-balancing?
FAQ
Q1: When does I2C need isolation, and how is it done?
I2C is an in-board short-distance bus; with reliable common ground it does not need isolation. Isolation is needed in three cases: the sensor or slave is on the high-voltage side (bus sampling AFE, high-voltage-box acquisition chips), inter-board or inter-pack communication (uncontrolled ground-potential difference), and safety requirement to isolate user-accessible interfaces from the internal high-voltage domain (meters, medical, industrial equipment). The practice is to choose a dedicated isolated I2C device (for example HOPERF CMT810X series, SCL/SDA bidirectional auto-direction recognition, both-side 1.8 to 5.5V level shift); the outside is still standard SCL/SDA pins with zero software change; check withstand on the dual caliber of test value and working voltage, and check speed and pull-up per step four of this article. Parameters follow the original manufacturer datasheet.
Q2: Why can a single one-way digital isolator not isolate I2C?
Because the I2C SDA is a bidirectional open-drain line: master write, slave acknowledge, multi-master arbitration and slave clock stretching all happen on the same line. A one-way isolator blocks the return direction, so the slave acknowledge cannot return to the master and the bus locks. UART / SPI have fixed signal flow and can directly use a one-way isolator; I2C must use either a dedicated isolated I2C device (direction logic done inside the chip) or two one-way isolators back-to-back plus discrete circuitry to split the bidirectional line into two directions — the latter has more components, larger loop delay and prone multi-slave arbitration problems, and is only considered when reusing inventory or modifying an old board.
Q3: How is the bidirectional direction of isolated I2C automatically recognized?
A dedicated isolated I2C device (for example HOPERF CMT810X) automatically judges the direction of the open-drain line inside the chip: whichever side pulls the line low, that low-level state is transmitted to the opposite side; when released the pull-up restores high, also transmitted across the barrier. To the master and slave the isolator is transparent — no direction-control pin is needed and no I2C driver code change is required. This is completely different from the fixed channel direction of a general digital isolator, and is the fundamental reason I2C isolation must use a dedicated device or back-to-back scheme. The setup time of direction switching and the propagation delay are given in the device datasheet; for high-speed mode include them in the timing budget.
Q4: Isolated I2C bus speed will not come up or the waveform is abnormal; how to troubleshoot?
Troubleshoot in three steps: waveform first, then timing, then power. Waveform level: a trailing rising edge means the pull-up resistor is too large or bus capacitance too large, so lower the pull-up (100kHz about 4.7kΩ, 400kHz about 2.2kΩ, high-speed about 1kΩ to start — all engineering estimates adjusted by bus capacitance), reduce the load and shorten traces; timing level: occasional NACK and clock-stretching timeout, first confirm the isolator propagation delay is within the timing budget, then check the slave clock stretching and MCU timeout config; power level: the isolation two-side power domains must be independent (CMT810X both-side VCC 1.8 to 5.5V each to its own), and communicating before the secondary supply is ready gives random anomalies, handled per the power-up sequence constraint. Follow the measured waveform and device datasheet.
Contact us
For I2C isolation and high-side sensor-communication device selection check (scheme comparison, withstand and package class, level-shift and pull-up values), HOPERF CMT-series sample application and domestic-replacement evaluation, please contact us.
Shenzhen Intek Technology Co., Ltd — authorized distributor of AMSEMI (TVS) and HOPERF (CMT-series digital isolators) Tel / WeChat: 136-3264-8484 Address: 4F, Building 2, Jingwei Center, No. 309 Ping'an Avenue, Pinghu Street, Longgang District, Shenzhen Website: www.intek.vip
Disclaimer: This article is technical popular-science and industry exchange content, for reference only, and does not constitute selection, procurement or other business-decision advice. The parameters of isolated I2C devices — bidirectional direction recognition, both-side level-shift range, speed class and isolation-withstand class — are taken from HOPERF official public materials (website product pages and datasheets) as typical or range examples, and differ significantly by model and operating condition; the pull-up resistor value vs speed relationship is an engineering-estimate order of magnitude, and actual design must follow the selected model original datasheet, bus-capacitance measurement and whole-system waveform.