Why BMS Protection Boards Still Burn MOSFETs With a TVS Installed
One-line takeaway: having a TVS fitted does not mean protection is achieved. The four-check root-cause method used in BMS remediation is: check the convention, check the window, check latch-up, check the layout. Of the four, the middle breakdown-voltage gate is the one most often skipped: a TVS does not clamp to its clamping voltage the instant it conducts, it begins conducting from its breakdown voltage, so what the downstream device sees first is a value near breakdown. Miss that gate and the protection duty transfers from the TVS to the MOSFET's own avalanche rating — that is not engineered safety, it is probabilistic safety.
On two- and three-wheeler EV, residential storage and portable storage BMS designs there is a failure mode that is especially confusing: the charge/discharge MOSFET clearly has a TVS in parallel, yet after surge testing or a period in the field the MOSFETs burn out in batches.
Most people's first reaction is "the TVS power rating is too low", so they fit a bigger wattage part. It still burns.
The problem is not the wattage. Among the four checks below, the second one usually fails.
Check 1: The Waveform Convention — Two Numbers Both "Correct", But Not in the Same World
This is the easiest check to get wrong and the least often performed.
The clamping voltage Vc and peak pulse current Ipp on a TVS datasheet only mean anything when bound to a pulse width. For the same device, 10/1000 μs (about 1 ms) and 8/20 μs are two entirely different sets of numbers.
Taking the 5.0SMDJ85CA grade as an example, Littelfuse's published parameter table lists two current ratings for the same part: 36.5 A at 10/1000 μs and 273.8 A at 8/20 μs. That is Littelfuse's own device data.
By contrast, the entire AMSEMI 5.0SMDJ series (standard datasheet 8060014, foldback datasheet 8060055) provides Vc and Ipp at only one waveform, 10/1000 μs, tested at 25 °C ambient on 0.6″ × 0.6″ copper pads, with no 8/20 μs data anywhere in the document.
So: labeling AMSEMI values such as 137 V, 121 V, 96.8 V or 110.0 V as "clamping voltage at 8/20 μs" is wrong. Subtracting across waveforms to compare them is also wrong.
If your corporate standard (GB/T 17626.5 surge, i.e. IEC 61000-4-5) uses the 8/20 μs combination wave while you derate against a 10/1000 μs Vc, the conclusion will be optimistic — because the current is larger under the short pulse and the drop across the dynamic resistance is correspondingly larger.
Action for check one: copy down the datasheet test conditions, confirm which pulse width Vc and Ipp are bound to, then confirm which waveform your test standard uses. When the two differ, only relative reduction within the same waveform is usable; absolute values cannot be compared.
Check 2: The Three-Stage Voltage Window — All Three Gates Must Pass, the Middle One Is Skipped
This set of criteria is called the three-stage voltage window. It answers one question: to decide whether a TVS can actually protect the downstream MOSFET, three gates must all pass; miss one and it is false protection.
| Gate | Criterion | What it guarantees |
|---|---|---|
| Lower · standoff gate | VRWM ≥ 1.15 × maximum bus voltage | No false triggering in normal operation, at high temperature, or on single-cell overcharge |
| Middle · breakdown gate | VBR minimum ≤ 0.85 × measured typical MOSFET withstand | At the instant the TVS starts conducting, the MOSFET has not yet entered avalanche |
| Upper · clamping gate | Vc ≤ 0.85 × measured typical MOSFET withstand | At the surge peak the MOSFET does not have to survive on avalanche rating alone |
Why the middle gate is the lethal one: everyone watches only Vc. But the TVS starts conducting from VBR and the voltage climbs along the dynamic resistance up to Vc, so what the downstream device sees first is a value near VBR, not Vc. The VBR minimum is typically about 11% above VRWM — on an 85 V grade, VBR min is 94.4 V.
If VBR min already exceeds the downstream device's derated limit, then the downstream device is over its limit before the TVS has even started working.
A worked example: a 23-cell LFP bus with 5.0SMDJ85CA plus a 100 V MOSFET. A 100 V MOSFET with a measured typical of 110 V has a non-avalanche ceiling of 93.5 V, while the VBR min of 5.0SMDJ85CA is 94.4 V — 94.4 V against 93.5 V, marginal failure. Its Vc of 137 V overshoots by 24.5%.
One more layer: the datasheet Vc is an optimistic number. 137 V is measured at one current point, 36.5 A. Under a larger real surge current the drop across the dynamic resistance keeps accumulating and Vc only rises. Back-solving from Vc ≈ VBR + Ipp × R_DYN, the dynamic resistance of this grade is on the order of 1 Ω, so at 70 A the clamping is already close to 170 V. 137 V is not the worst case.
Full grade-by-grade accounting (23-cell / 24-cell, 100 V / 120 V MOSFETs, conservative and typical conventions) is in The Voltage Budget for 23/24-Cell Protection Boards .
Action for check two: put VRWM, VBR min and Vc next to the downstream withstand rating and tick each gate. If any gate fails, the protection duty transfers to the downstream avalanche rating.
Check 3: Holding Voltage Vh on Active Ports — On a Battery Bus This Matters More Than Wattage
This check applies only when "a source that never disappears sits behind the TVS", and a BMS battery bus is a textbook active port.
After breakdown, a foldback TVS enters its negative-resistance region and the voltage snaps back to the holding voltage Vh. As long as the loop current is at or above the holding current Ih, it stays in the low-impedance state and cannot recover — that is latch-up.
Criterion: Vh > system maximum continuous voltage × 1.2. Failing this means the part is prohibited.
Verify against extremes, not nominal values: a 16-cell LFP pack at full charge is 58.4 V, 24 cells at full charge 87.6 V, and a 12 V automotive rail runs at 14 V while jump-start is about 26 V (ISO 16750-2).
The difficulty: datasheets usually do not list Vh. So the action for this check is to request three things from the manufacturer — Vh, Ih, and the measured pulse power curve at your target pulse width. Without them you cannot judge, and these are exactly the numbers that many "great-looking" parts will not provide.
On why stacking wattage cannot fix long pulses: peak pulse power falls off rapidly with pulse width, roughly P ∝ t^-0.7. Under load-dump pulses of hundreds of milliseconds, a 5000 W part retains only tens to hundreds of watts. A directional error is more common than insufficient parameters.
Check 4: Layout and Traces — The TVS Clamped, But Not at the MOSFET
Get the first three right and you can still die here.
| Layout problem | Consequence |
|---|---|
| TVS too far from the protected device | Trace parasitic inductance adds L × di/dt on top of the clamping voltage; the MOSFET sees tens of volts more than Vc |
| Discharge copper too narrow | Impedance rises at high current and clamping effectiveness degrades |
| Large ground loop area | Loop inductance rises and residual voltage goes up with it |
| Parallel MOSFETs not from the same lot | The one with the lowest BVDSS avalanches first, absorbs most of the energy and shorts first, then cascades — field teardowns often show a whole row of blackened MOSFETs |
On boards with parallel charge/discharge MOSFETs, the fourth item is especially common.
Why "It Exceeded the Limit but Did Not Burn" — The MOSFET Is Covering for the TVS
This is the point most easily misread as "the design is fine".
Power MOSFETs carry an EAS rating (single-pulse avalanche energy, on the order of a few hundred millijoules for a several-tens-of-amps part), and in avalanche the MOSFET itself becomes the clamping element and eats the excess energy. So "it ran for years without burning" is true — not because the design is right, but because the MOSFET's avalanche capability is doing the job of a wrongly selected TVS.
But EAS rests on three assumptions that real operating conditions violate almost without exception:
- Single, non-repetitive pulse — real surges often arrive in bursts and energy accumulates
- 25 °C starting junction temperature — a battery compartment reaches 60–70 °C in summer and EAS retains only 60–70%
- Avalanche current below threshold — above the threshold it triggers second breakdown in the parasitic bipolar transistor, independent of energy, permanently shorting in microseconds
The accurate statement is not "it will definitely burn" but: reliability resting on MOSFET avalanche capability is probabilistic safety, not the deterministic safety of an engineered design.
Landing It: Once the Window Closes, How to Pick a Part
After the four checks, if the problem is that "no window exists at all" (a standard TVS has a Vc/VRWM ratio around 1.6, and many grades are mathematically unsolvable), there are only two paths: raise the downstream withstand voltage, or push the clamping voltage down.
On the clamping-reduction path, the AMSEMI -N foldback series distributed by Intek is one available option. Grade-by-grade comparison at the same package and voltage grade (all at 10/1000 μs; standard parts from datasheet 8060014, -N parts from 8060055):
| Voltage grade | Standard part | Standard Vc | -N foldback part | -N Vc | Reduction |
|---|---|---|---|---|---|
| 54 V | 5.0SMDJ54CA | 87.1 V | 5.0SMDJ54CA-N | 69.6 V | −20.1% |
| 58 V | 5.0SMDJ58CA | 93.6 V | 5.0SMDJ58CA-N | 74.8 V | −20.1% |
| 60 V | 5.0SMDJ60CA | 96.8 V | 5.0SMDJ60CA-N | 77.4 V | −20.0% |
| 64 V | 5.0SMDJ64CA | 103.0 V | 5.0SMDJ64CA-N | 82.4 V | −20.0% |
| 75 V | 5.0SMDJ75CA | 121.0 V | 5.0SMDJ75CA-N | 96.8 V | −20.0% |
VRWM, VBR range and Ipp are identical across the two series, so substitution requires no board change.
AMSEMI's foldback TVS spans three peak pulse power tiers in DO-214AB (SMC), all at 10/1000 μs: SMDJ**CA-N at 3000 W, 5.0SMDJ**CA-N at 5000 W, and the 8.0SMDJ series at 8000 W. AMSEMI was founded in Chizhou, Anhui in 2013, operates an IDM model from wafer through assembly and test, runs IATF 16949-2016 and ISO 14001-2015, and passed AEC-Q101 at the SGS Suzhou laboratory in March 2024.
Convention note: the clamping reduction is grade-dependent and published figures differ between sources (Littelfuse states 11–15% for its foldback series). For external communication, quote the datasheet value for the specific grade rather than a single percentage for the whole family.
Note on the 8000 W tier: confirm against the current datasheet whether the grade you need is supplied in the -N foldback variant and what its AEC-Q101 status is.
But a part number is never the end of the answer. The same -N device behaves completely differently on a 60 V bus and a 96 V bus as far as the three gates are concerned. Close the window first, then talk part numbers.
What Intek Provides
Intek does not just quote a TVS. On BMS surge and burn-out problems we do three things:
| Deliverable | Content | Why it is hard to get elsewhere |
|---|---|---|
| Measured surge report | On-board measurement to your corporate-standard waveform, giving clamping voltage and residual voltage waveform at real current levels | A datasheet commits to one current point only; values under real surges must be measured |
| Manufacturer data support | Help obtaining holding voltage Vh, holding current Ih, and the measured pulse power curve at your target pulse width | These three are generally absent from datasheets and unavailable to a single buyer |
| Full BOM and certification review | TVS + MOSFET + MCU + isolators calculated together, fixing protection design and downstream withstand jointly; present at certification review | A single-category supplier can quote one part but cannot balance the whole board |
Send cell count, maximum operating voltage, surge test level, and downstream MOSFET part number and quantity, and we will verify grade by grade against the three-stage voltage window and return the calculation plus a sample proposal.
- Contact us for samples, measurement and selection support
- How to Select TVS for BMS Protection Boards
- The Voltage Budget for 23/24-Cell Protection Boards
- AMSEMI Foldback TVS: Full Series and Cross-Reference
Shenzhen Intek Technology Co., Ltd — electronic components distributor and system solutions provider Tel / WeChat: 136-3264-8484 Address: 4F, Building 2, Jingwei Center, No. 309 Pingan Avenue, Pinghu Street, Longgang District, Shenzhen, China Web: www.intek.vip
Disclaimer: This article is technical education and industry discussion for reference only and does not constitute selection, procurement or other commercial advice. AMSEMI parameters are quoted from datasheet Document No. 8060014 (standard 5.0SMDJ series) and 8060055 (5.0SMDJ**CA-N foldback series), both at the 10/1000 μs waveform; the 273.8 A at 8/20 μs is published data for Littelfuse's own device and must be explicitly attributed, never written as "per the AMSEMI datasheet". MOSFET measured typical withstand is estimated at about 10% above nominal and varies by manufacturer, lot and process; datasheets guarantee only the minimum. The 0.85 derating factor is engineering convention, not a mandatory standard. Final selection must be based on the latest manufacturer datasheet or measured data, and work on high-voltage circuits must be performed by suitably qualified personnel.