Isolation Done but Useless? Isolation Barrier PCB Layout, Creepage Distance and Secondary-Side Isolated Supply

Bottom line: picking the right isolator does not mean the isolation is actually made. Across-barrier layout comes down to three things, and any one done wrong invalidates the whole link: first, the area under the isolation barrier (isolation gap) must be kept clear — copper pour, traces, vias or silkscreen crossing the barrier all shorten the effective creepage distance, and a prototype may pass while safety testing fails right here; second, creepage distance and clearance cannot be taken directly from the device marked 5kVrms — they must be looked up in the standard table by "working voltage × pollution degree × material group × insulation type", because 5kVrms is only the UL1577 withstand test value; third, the secondary side must have a truly isolated supply — drawing from the primary or relying on a bootstrap reconnects the two grounds, voiding the isolation. Below, these three points give actionable routing rules, a secondary-supply comparison and a power-up sequence checklist. Device parameters are taken from HOPERF official materials as typical or range examples; the original datasheet governs.

flowchart TD
    A["Locate the barrier first<br/>set keep-out width by package"] --> B["Mark keep-out zone<br/>no copper / no trace / no via / no silkscreen inside"]
    B --> C["Each side forms its own loop<br/>primary returns to primary ground, secondary to secondary ground, no bridge"]
    C --> D{"Creepage and clearance<br/>enough by standard table?"}
    D -- "Not enough" --> E["Widen keep-out / wider-body package<br/>or slot / change material group"]
    E --> D
    D -- "Enough" --> F["Decoupling caps both sides<br/>close to VDD pin"]
    F --> G["Secondary must have isolated supply<br/>no primary draw or bootstrap"]
    G --> H["Common-mode loop and CMTI check<br/>verify separately in high-dv/dt"]
    H --> I["Power-up sequence and fail-safe<br/>default output suffix / diagnostic pin"]

First, two high-frequency questions

Q: The isolator is selected correctly per the datasheet — why is isolation still "not actually made"?

Because isolation is a layout behavior, not a device attribute. An isolator's isolation is guaranteed by the dielectric between the two dies (the SiO2 capacitive isolation barrier), but it only covers the few millimeters of the package body; beyond the package, the distance between the two electrical domains is set by your PCB. The three most typical "wasted" cases in engineering: first, copper / traces / vias under the barrier short the surface creepage path, so the marked withstand is unusable; second, the two-side ground planes are "connected once" with a 0Ω resistor, ferrite bead or a trace, re-attaching the common-mode blocking path; third, the secondary relies on primary power or a bootstrap, binding the two domains through the supply reference. All three share one feature — functional tests all pass (signals still go through), and the problem only shows up in safety testing, a humid / dusty environment, or a high-dv/dt field. Which positions need isolation and which device to use where, see Which positions in an energy-storage system actually need isolation?.

Q: Why is the "secondary-side isolated supply" the easiest item to miss in isolation design?

Because many designers put all their attention on the signal-isolation device and assume "power will sort itself out", only to find at layout time that the secondary has no usable isolated rail. The two common compromises both destroy isolation: first, drawing a branch from the primary supply — the reference ground connects and isolation fails; second, using a non-isolated high-side bootstrap for the secondary — essentially a floating supply within the same domain, so common-mode blocking is equally absent. The correct approach is to treat the secondary isolated supply as a required component of isolation design, planned together with the main / auxiliary supply for capacity and windings at the selection stage. For on-board isolated auxiliary-supply design, flyback turns ratio and clamp design, see How to make an on-board auxiliary supply?.

Step 1: how to draw the barrier — the keep-out zone is the start of the layout

The first thing in cross-barrier layout is not routing, but first drawing a band with nothing in it. The band width is based on the creepage distance of the isolator package body; run this band from end to end of the board (do not just open a small notch near the isolator), then constrain all elements on both sides from entering the band.

Common violation	Surface symptom	Actual consequence	Correct practice
Copper pour or copper shaping under the barrier	Appears and functions normal	Surface path shorted, withstand and creepage tests fail	Place no copper in the keep-out; both-side pours end cleanly at the band edge
Trace or differential pair crossing the band (incl. passing underneath)	Signal passes normally	Effective creepage reduced to only the package segment; common-mode current gets a bypass	All cross-band signals go through the isolator body; others route around
Via (incl. ground via, stitching via) in the band	No sensation	Same as copper pour — inserts a conductor on the surface	Stitching vias leave clearance at the band edge; absolutely no via in the band
Silkscreen, designator, test point over the band	No sensation	Silkscreen is a semi-conductive contaminant; test points directly connect	Move silkscreen and test points outside the band; even retained silkscreen needs clearance
Device body crossing the band (e.g. a resistor spanning the two grounds)	Functions normally	Directly connects the two domains; isolation fully fails	Cross-domain connection only through an isolation device

How wide the in-band keep-out is directly decides which package you can choose later. Narrow-body and wide-body packages typically correspond to about 3.75kVrms and 5kVrms with package creepage of about 4mm and 8mm — the keep-out must at least follow the package, otherwise the package gives you 8mm of creepage but the board leaves only 3mm, and the bottleneck moves to the PCB. Exact values follow the selected device datasheet and safety certificate; for the package-to-withstand mapping see What does 5kVrms on an isolator mean?.

Step 2: each side forms its own loop — the ground plane must not be bridged

Treat the two sides of the barrier as two independent electrical systems: the primary signal return goes to the primary ground, the secondary signal return goes to the secondary ground, and the only connection between the two grounds is the isolator body.

Three actionable points:

1. Decoupling caps close to the pins: primary VDD decoupling returns to primary ground, secondary VDD decoupling returns to secondary ground, and the cap-to-pin distance must be short — once the decoupling loop goes around, the high-frequency return finds another path (e.g. through the parasitic capacitance of the isolation barrier), effectively opening the door to common-mode interference.
2. Do not "connect the two grounds once": 0Ω resistors, ferrite beads, small capacitors, single-point vias — any component that connects the two grounds on the board voids the isolation. To handle ESD and common-mode issues, use the Y-capacitor / chassis path (see Step 5), not a short between the two grounds.
3. Minimize the number of cross-band signals: each extra cross-band signal is another potential common-mode injection and creepage-shortening point. Where a serial bus (e.g. isolated UART / SPI / CAN) can replace parallel multi-line, merge first. For bus-side device selection see How to select isolated CAN and RS-485 transceivers?.

Step 3: how to look up creepage distance and clearance in the table

These two terms are often mixed up, but they measure different things:

• Creepage distance: the shortest path measured along the insulating surface. It fears surface contamination and moisture-induced tracking, so it strongly relates to pollution degree and material group.
• Clearance: the shortest spatial distance between two conductors. It fears air breakdown, so it strongly relates to voltage peak and altitude (air pressure), and little to pollution.

System requirements are decided by looking up the table from four elements, not by the device marked withstand:

Table element	Common engineering value	Effect direction
Working voltage	The long-term RMS voltage at that isolation point (not bus peak, still less the test voltage)	Higher voltage → larger requirement
Pollution degree	Clean, controlled control boards usually pollution degree 2; potting or full sealing can relax	Heavier pollution → larger requirement
Material group	Board grouped by CTI (ordinary FR-4 often falls in a lower group)	Lower group → larger requirement
Insulation type	Functional / basic / reinforced (safety-related isolation is mostly reinforced)	Reinforced → largest requirement

The use of this table is reverse-constraining the layout: first look up the required creepage from the actual conditions, then reconcile with what the selected isolator package can provide.

Isolator package	Isolation-withstand level (typical)	Package creepage order of magnitude	When you must change
Narrow body	about 3.75kVrms	about 4mm	System table value exceeds package value, or higher working isolation voltage needed
Wide body	about 5kVrms	about 8mm	Safety-related isolation at high bus voltage, certification projects prioritized

Two engineering reminders:

• 5kVrms is not the basis for creepage. It is the UL1577 isolation-withstand test caliber (about one minute of applied voltage without breakdown); to check long-term working voltage you look at parameters like working voltage / operating isolation voltage. Using the test value as the working voltage or as the creepage basis is the most common selection mistake; see What does 5kVrms on an isolator mean?.
• Slot width must meet the standard minimum. Cutting a through-slot in the middle of the barrier significantly increases the surface path length, but the slot width must meet the standard's minimum; otherwise that segment is still counted as a straight line, wasting the slot and sacrificing creepage margin.

Step 4: how to power the secondary-side isolated supply

This is the most easily missed section of the whole article. Four common implementations of the secondary isolated supply:

Supply method	Typical capability order	Isolation source	Trade-off
Isolated DC-DC module	Fixed-output 1W / 2W class, e.g. 5V to 5V	Internal transformer of the module	Most convenient, complete certification data; average efficiency, mid-to-high cost and board area
Multi-winding output of main/aux supply	Add one secondary winding to the flyback transformer	Shares the same transformer with the main supply	Best cost, high utilization; requires planning turns ratio and winding isolation early, high rework cost
Isolated supply IC + small transformer	Hundreds of mW to 1W class	IC internal push-pull driving an external transformer	Small size, customizable multi-output; high transformer selection and layout demands
Bootstrap / primary direct draw	Can only supply a same-domain floating supply	No isolation	Secondary via this method voids isolation; only for non-isolated high-side drive

Capacity accounting must be done on three books together, not just the average:

1. Steady-state current book: sum the operating currents of all devices powered by this secondary isolated supply (isolator, isolated sensing, isolated-driver quiescent current, surrounding amplifiers and comparators), then leave margin.
2. Peak-current book: at the isolated gate-driver turn-on / turn-off instant it must provide peak source/sink current (HOPERF CMT8602X is 4A peak source / 6A peak sink class); the secondary supply and decoupling must survive the instantaneous drop, otherwise it shows as weak drive and rising switching loss.
3. Decoupling book: place a decoupling cap close to each device VDD pin, including the secondary. When decoupling is insufficient, the secondary voltage collapses at the switching instant and the isolator may show false output toggling.

For secondary-supply and CMTI reconciliation of isolated gate drivers see How to select an isolated gate driver?; for secondary supply and fail-safe output of high-side sensing chains see How to do high-side current sensing?.

Step 5: common-mode loop and CMTI — give the common-mode current a way home

The isolation barrier is capacitive (SiO2 capacitive isolation barrier) with parasitic capacitance across it. When the primary sees high dv/dt (e.g. power-device switching, bus surge), displacement current is injected into the secondary through this parasitic capacitance — the isolator can block DC and low-frequency common-mode, but it cannot make high-frequency common-mode current vanish out of thin air; it can only keep the current outside the barrier, and only if that current has a low-impedance return path. If it finds none, it makes its own: through the secondary circuit, through the communication line, through the sensing line, showing as bit-errors, false triggering or device damage.

Four actions in high-dv/dt situations	What to do	Why
Give the common-mode current a return path	Properly set Y-capacitor, transformer shield, chassis and ground path	Let the common-mode current take the designed low-impedance path, not through the signal loop
Reconcile device CMTI margin	Compare the datasheet CMTI minimum with the system-measured dv/dt	Look at the guaranteed minimum, not just the typical
Reduce coupling area and loop area	Keep cross-band traces short, signal and return paths paired and close	Larger area → stronger coupling; longer return path → larger common-mode drop
Coordinate isolation with surge protection	Isolator handles common-mode and ground-potential difference, TVS handles transient surge energy	They are complementary; an isolator still needs a TVS

Common CMTI reference orders (HOPERF official data): general digital isolators CMT812X typically ±200kV/μs, CMT826X typically ±250kV/μs, isolated gate driver CMT8602X minimum ±150kV/μs. The selection principle is compare the minimum value with the worst case, not the typical. For isolation and TVS division of labor see RS485 / CAN communication port keeps failing — what to do? and How to do surge protection for energy-storage / BMS products?.

Step 6: power-up sequence and fail-safe

Beyond layout, two more things strongly related to cross-barrier design must be fixed at the schematic stage:

1. Power-up sequence: confirm whether the selected device requires an order between the two-side supplies; when the two supplies are not synchronized, the isolator may output a narrow pulse at power-up, and without filtering or confirmation the downstream may mistake it for a valid signal (e.g. falsely trigger a drive once or falsely report a communication frame). The robust approach is to have the downstream mask the input within a fixed window after its own supply is established, or choose a model insensitive to power-up/down order.
2. Default output state and diagnostics: the default output suffix (HOPERF CMT series suffix 1 = default output high, 0 = default output low) must align with "stop the load or hold on failure"; devices with diagnostic / fail-safe output must have the diagnostic pin connected to the MCU and written into the state machine — leaving it floating is the same as not having it. Designs migrated from optocouplers are especially prone to fail here; see Can an optocoupler be replaced directly by a digital isolator?.

Common pitfalls

Pit	Symptom	Correct practice
Copper / trace / via under the barrier	Functions normally, withstand and creepage tests fail	No copper, no trace, no via, no silkscreen in keep-out; only the isolator crosses
Two grounds "connected once" with 0Ω or ferrite	Isolation nominal, common-mode still enters	No bridge between grounds; use Y-capacitor and chassis path for common-mode
Secondary from primary draw or bootstrap	Isolation fails, output varies with primary load	Give the secondary its own isolated supply; capacity on steady + peak + decoupling books
Using 5kVrms as creepage basis	Looks enough at selection, fails the standard table	Look up by working voltage, pollution degree, material group, insulation type
Slot width below standard minimum	Thought distance was added, actually not counted	Make slot width per standard, otherwise the segment counts as straight
CMTI only on typical value	Bit-errors / false trigger in high-dv/dt field	Compare datasheet minimum with measured worst dv/dt; else change model or reduce dv/dt
Diagnostic and fail-safe pins floating	Isolation-link failure read as normal	Connect diagnostic pin to MCU and define system-level failure action

Related solutions

• Isolation position planning: Which positions in an energy-storage system actually need isolation?
• Isolation-withstand dual caliber: What does 5kVrms on an isolator mean?
• Full-category isolator selection: How to select digital isolators?
• Gate-driver isolation selection: How to select an isolated gate driver?
• Isolated sensing and secondary supply: How to do high-side current sensing?
• Bus isolation and node count: How to select isolated CAN and RS-485 transceivers?
• Optocoupler replacement migration: Can an optocoupler be replaced directly by a digital isolator?
• On-board isolated auxiliary supply: How to make an on-board auxiliary supply?
• Isolation and TVS division: RS485 / CAN communication port keeps failing — what to do?, How to do surge protection for energy-storage / BMS products?
• BMS protection-side voltage window and device coordination: How to select BMS protection-board TVS?, How to calculate the TVS and MOS voltage window for a 23 / 24-cell battery pack?
• Secondary-supply device thermal check: IGBT / MOSFET overheating — what to do?

FAQ

Q1: Why must the PCB under the isolation barrier (isolation gap) be kept clear, and what happens if copper or traces cross it?

Because creepage distance is the shortest path measured along the insulating surface, and the area under the isolation barrier is exactly where the two electrical domains are closest on the surface. Pouring copper, running a trace, drilling a via or printing silkscreen under the barrier is like placing a conductive or semi-conductive path on the surface path, shortening the effective creepage distance to only the package body, so the isolator marked withstand voltage cannot be used. Typical symptoms are a prototype that functions perfectly but fails the insulation-withstand and creepage tests, or leaks or bit-errors in the field under high humidity and dusty pollution. The correct practice is to use the isolator package body width as the keep-out width, and in that area place no copper, no trace, no via, no silkscreen and no test point on either side; any signal that must cross goes through the isolator body itself. The exact keep-out width follows the creepage value in the selected device datasheet and the system safety standard.

Q2: How to calculate creepage distance and clearance, and can the isolator marked 5kVrms be used directly as the creepage basis?

It cannot be applied directly. A number like 5kVrms is the UL1577 component-level certification isolation-withstand test value (about one minute of applied voltage without breakdown); it describes how high an instantaneous test voltage the insulation can withstand, not how long the surface path must be. Creepage distance (measured along the insulating surface) and clearance (measured as the shortest spatial distance) are determined by looking up the standard table from four elements: first, the working voltage (not the bus peak, nor the test voltage); second, the pollution degree (a clean control board is usually pollution degree 2); third, the material group (the board material grouped by CTI); and fourth, the insulation type (functional, basic or reinforced). The looked-up result is not necessarily equal to the package creepage distance; when the system requirement exceeds what the package gives, the only options are a wider-body package, a wider keep-out or a changed insulation structure. Slotting is a common distance-increasing method, but the slot width must meet the standard minimum width, otherwise that segment is still counted as a straight line. Narrow-body and wide-body packages typically correspond to about 3.75kVrms and 5kVrms with package creepage of about 4mm and 8mm; exact values follow the datasheet and safety certificate.

Q3: How to power the isolator secondary side, and why not draw from the primary or rely on a bootstrap?

Both sides of the isolator must be powered by supplies of their own electrical domain: the primary uses a primary-ground-referenced supply, the secondary must use a secondary-ground-referenced isolated supply (isolated DC-DC module, multi-winding output of a main/auxiliary supply, or an isolated supply IC with a small transformer). Drawing directly from the primary, or powering the secondary with a high-side bootstrap, reconnects the two sides power-reference grounds, the common-mode blocking of the isolation barrier disappears, and the practical result is no isolation. The secondary isolated supply is the most commonly missed design item; typical symptoms are abnormal isolator operation, output level fluctuating with primary load, bit-errors, or a scope measurement showing the two sides are actually connected through ground. In design, also account for three capacity items: the sum of operating currents of the powered devices, the peak source/sink current when the isolated gate driver switches, and whether each decoupling capacitor is placed close to the device pin; insufficient capacity or poor decoupling makes the secondary voltage collapse at the switching instant, showing as weak drive or false triggering. Parameters follow the original manufacturer datasheet and whole-system measurement.

Q4: Isolation is done but still bit-errors and gate-driver failure; what to check first in the layout?

Check in four ordered steps: first, verify the isolation actually holds, using a multimeter and withstand tester to confirm the two-side grounds are not connected and there is no copper or via crossing the keep-out; second, look at the secondary supply, measuring whether the secondary voltage collapses at the switching instant and under full load, and whether decoupling is close; third, look at the common-mode loop, where in high-dv/dt situations the parasitic capacitance of the isolation barrier injects common-mode current into the secondary, so the chassis, Y-capacitor and shield must give a low-impedance return path, and compare the datasheet minimum CMTI with the measured common-mode dv/dt (HOPERF CMT812X typically ±200kV/μs, CMT826X typically ±250kV/μs, isolated driver CMT8602X minimum ±150kV/μs) — if insufficient, only a higher-CMTI device or reduced dv/dt works; fourth, look at the return path and ground plane, where the primary and secondary ground planes must not be bridged with a 0Ω resistor or ferrite bead, and only the isolator body crosses the barrier. When locating, prefer waveforms over guessing devices, because common-mode interference and layout problems cannot be solved by changing the model. Diagnostic and fail-safe output pins must be connected to the MCU and written into the state machine. Exact values follow the original manufacturer datasheet, safety standard and whole-system measurement.

Contact us

For cross-barrier PCB layout review (keep-out planning, creepage-distance vs package selection reconciliation, secondary isolated-supply capacity accounting, common-mode loop and CMTI margin check), HOPERF CMT-series sample application and domestic-replacement evaluation, please contact us.

Shenzhen Intek Technology Co., Ltd — authorized distributor of AMSEMI (TVS) and HOPERF (CMT-series digital isolators) Tel / WeChat: 136-3264-8484 Address: 4F, Building 2, Jingwei Center, No. 309 Ping'an Avenue, Pinghu Street, Longgang District, Shenzhen Website: www.intek.vip

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Disclaimer: This article is technical popular-science and industry exchange content, for reference only, and does not constitute selection, procurement or other business-decision advice. The isolation-device parameters (CMTI, drive capability, isolation withstand, package creepage order of magnitude, etc.) are taken from HOPERF official public materials (website product pages and datasheets) as typical values or range examples, and differ significantly by model and operating condition; the specific values of creepage distance and clearance must be looked up in the tables of IEC 60664-1, IEC 62368-1, GB 4943.1 and other standards based on the actual working voltage, pollution degree, material group and insulation type — the orders of magnitude given in this article are not a design basis; the secondary isolated-supply capacity accounting and common-mode loop design are engineering-method explanations, and the actual design must follow the selected model original datasheet, safety standard and whole-system measurement.