How to Design a MOSFET Gate Drive Circuit: Gate Resistor, Miller Plateau and False Turn-On
Bottom line: a drive circuit has to satisfy four things at once — turn on fast enough (low switching loss), turn off hard enough (no false turn-on), keep the loop clean enough (no ringing), and keep the gate safe (no overvoltage). Engineering practice works in five steps: set the drive voltage platform from device class, size peak drive current and drive power from total gate charge Qg, take separate turn-on and turn-off resistors, check dv/dt Miller false turn-on, and finally review gate loop layout and common source inductance. The three field complaints "MOSFET runs hot", "both devices in the half bridge blow" and "the driver IC is hot" are almost never caused by bad parts; they are caused by a drive loop that was not designed properly.
flowchart TD
A["1. Set the drive voltage platform<br/>device class / gate oxide rating / threshold"] --> B["2. Read the Qg curve<br/>peak current and drive power"]
B --> C["3. Select the driver IC<br/>peak capability and average power both adequate"]
C --> D["4. Separate turn-on and turn-off resistors<br/>asymmetric drive"]
D --> E["5. Check dv/dt Miller false turn-on<br/>estimate and measure the VGS spike"]
E --> F{"Spike below half the threshold?"}
F -- "no" --> G["Improve turn-off loop / negative bias<br/>active Miller clamp"]
G --> E
F -- "yes" --> H["6. Gate loop layout<br/>loop area / Kelvin source"]
H --> I["Bridge dead time and body diode check"]
I --> J["Validate by measured waveforms and temperature rise"]First, the two questions asked most often
Question: what gate resistor value in ohms? There is no universal value. The gate resistor is essentially a balance point between switching loss, dv/dt and EMI, and gate ringing, and typical designs land between a few ohms and a few tens of ohms. The method is: estimate peak current from the datasheet Qg curve, start from a small value, then increase it while watching VGS and VDS until the ringing disappears and switching loss is still acceptable. Turn-on and turn-off normally use separate values, with the turn-off resistor generally smaller than turn-on.
Question: why does my MOSFET keep running hot? Classify the loss before changing parts: conduction loss equals I squared times hot RDS(on), while switching loss is proportional to Qg times switching frequency. If heating rises noticeably with switching frequency, the problem is drive capability and gate resistance, and a higher-current part will not help. If heating is largely independent of frequency, it is a conduction loss and heatsinking problem. MOSFET selection and paralleling for the BMS power path is covered in How to Select Charge and Discharge MOSFETs for a BMS Protection Board.
Step 1: set the drive voltage platform first
Drive voltage is not "as high as you can get". It is decided by device class, gate oxide rating and threshold voltage together. The same MOSFET can differ by more than a factor of two in on-resistance between different VGS values, and datasheets often list RDS(on) at several drive voltages.
| Device class | Common drive voltage (on / off) | Design notes |
|---|---|---|
| Logic-level low-voltage MOSFET | 4.5 V and 10 V grades (common) | Direct drive from 3.3 V or 5 V requires a logic-level type, with RDS(on) checked at the low level |
| Standard low- to mid-voltage MOSFET | About 10 V (commonly 8 to 12 V) | Gate-source limit commonly plus or minus 20 V; leave margin on a 12 V drive |
| Superjunction / high-voltage MOSFET | About 10 to 12 V | Smaller Miller capacitance and faster switching raise the dv/dt false turn-on risk |
| IGBT | About plus 15 V on, minus 5 to minus 8 V off | Negative turn-off bias prevents shoot-through; gate-emitter limit commonly plus or minus 20 V |
| SiC MOSFET | About plus 18 V on, minus 3 to minus 5 V off | Gate oxide reliability is sensitive; exceeding the recommended range risks long-term reliability |
The table gives commonly recommended industry values, but devices differ significantly between manufacturers and generations. Real design must return to the recommended operating range and absolute maximum ratings in the manufacturer datasheet; do not extrapolate from "all similar devices work this way".
Step 2: drive capability is set by Qg, not by the current rating
Two numbers decide the driver IC, and both are set by Qg:
- Peak current:
Ig peak is approximately (V drive minus V plateau) divided by (Rg external plus Rg internal). Rg internal is the internal gate resistance in the datasheet (commonly a fraction of an ohm to a few ohms). Example: a 10 V drive swing, Miller plateau of about 4 to 5 V, 10 ohms external and 2 ohms internal gives a peak current of about 0.4 to 0.5 A. The peak output capability of the driver must exceed this, otherwise the VGS rise is flattened and switching slows. - Average drive power:
P gate is approximately Qg times fsw times delta VGS. This decides whether the driver IC heats and how large the bootstrap or isolated supply must be. Example: Qg of 100 nanocoulombs, fsw of 100 kilohertz, delta VGS of 10 V gives about 0.1 W per device (100 nC times 100 kHz times 10 V); a three-phase bridge with six devices reaches about 0.6 W, and paralleled devices multiply it again — which is the most common reason a driver IC runs hot.
Two common mistakes: checking peak current but not average power (fine at low frequency and high current, hot as soon as frequency rises); and assuming a larger driver current is always better (an excessively fast gate edge brings dv/dt and ringing problems that still have to be pulled back with the gate resistor and loop layout).
Step 3: separate turn-on and turn-off resistors
With a single resistor, turn-on and turn-off share one value and cannot satisfy two opposing requirements. Standard practice is asymmetric drive with a diode plus resistor: turn-on goes through Rg on (larger), turn-off through Rg off (smaller, or a diode for fast discharge).
| Adjustment | Benefit | Cost | When it is needed |
|---|---|---|---|
| Larger gate resistor | Lower dv/dt and di/dt, easier EMI, smaller reverse recovery spike | Higher switching loss, tighter dead-time budget | Failing EMI tests, long harnesses or transformers, large body diode reverse recovery spikes |
| Smaller gate resistor | Lower switching loss, higher efficiency | More ringing and overshoot, higher false turn-on risk | High frequency, efficiency-first designs |
| Smaller turn-off resistor alone | Faster turn-off, shorter Miller false turn-on window | Higher turn-off VDS overshoot | Half bridge legs, paralleled devices |
| Individual gate resistor per device | Suppresses circulating current and parasitic oscillation between paralleled devices | More board area and more drive power | Paralleled devices (see MOSFET Paralleling Design for Charge and Discharge Paths) |
Step 4: the Miller plateau and dv/dt false turn-on (the step that destroys devices most often)
Mechanism: when the high-side device of a half bridge turns on, the drain-source voltage of the low-side device rises rapidly. That high dv/dt couples a displacement current through the Miller capacitance Cgd of the low-side device, which flows through the gate loop (including the turn-off loop impedance) to the source and develops a voltage across the impedance. If that voltage lifts the gate of the device that should be off above the threshold, the low-side device conducts briefly, shoot-through occurs, and the devices can be destroyed within microseconds.
Order-of-magnitude estimate: I cgd = Cgd times dv/dt, VGS spike is approximately I cgd times Rg off (including driver pull-down impedance), and VGS spike must stay clearly below VGS(th) (engineering practice suggests holding it under half the threshold).
Caution: Miller capacitance Cgd varies non-linearly with drain-source voltage and the datasheet value is typical for a specific test condition, so this formula gives an order of magnitude and a risk direction only, not an exact result. The final answer is the measured VGS waveform, especially the gate spike at the instant the other device in the leg switches.
Mitigations in order of value:
| Mitigation | Principle | Cost | Where it applies |
|---|---|---|---|
| Reduce turn-off loop impedance | Lowers the voltage developed by the displacement current across the gate loop | Faster turn-off, higher turn-off overvoltage and EMI | Low-voltage half bridges, paralleled BMS power paths |
| Negative turn-off bias | Uses a negative bias to pull the gate away from the threshold | Needs a negative or isolated supply; gate oxide margin must be recalculated | IGBT, SiC, medium and high voltage legs |
| Active Miller clamp | Clamps the gate through a low-impedance path during switching | Requires a driver IC with this function | High-frequency, high-current half bridges |
| Add gate-source capacitance | Raises the effective gate impedance, reducing the voltage lift | Slower switching, higher drive power | Low power, slow switching, no high-frequency requirement |
Key judgement: "switch fast" and "resist Miller false turn-on" are inherently opposing requirements, so set the priority first and then tune, otherwise you fall into the loop of "add resistance, then add snubber, then change resistance again". SiC devices are more sensitive to the drive loop; see Can a SiC MOSFET Replace an IGBT (Chinese) for the differences.
Step 5: gate loop layout and common source inductance
Correct parameters can still fail through layout, and this layer is overlooked more often than resistor selection:
- Keep the gate loop area small: driver to gate resistor to gate to source and back to the driver. The smaller this loop area, the lower the parasitic inductance and the less the ringing. Place the gate resistor as close to the driver as possible, not next to the MOSFET.
- Common source inductance: inductance in the power source trace develops a voltage as switching current changes, which acts as negative feedback that slows switching and causes oscillation. For high current, use a Kelvin source connection, separating the drive return and the power return into different paths at the device pins.
- Decoupling and bootstrap: place the driver VCC decoupling capacitor right at the pins. A rule of thumb for the bootstrap capacitor is about twenty times Qg or more, but bootstrap diode leakage and its own switching loss must be included — calculate it with the recommended formula in the driver datasheet.
- Paralleled devices: individual gate resistor per device and a symmetrical PCB, as covered in MOSFET Paralleling Design for Charge and Discharge Paths.
- Backstop for turn-off overshoot: a clamping device can limit drain-source overshoot at turn-off, but the clamp voltage must fall inside the MOSFET rating. The selection logic is the same as in How to Select a Low-Clamping TVS for a BMS Protection Board (Chinese) — a clamp voltage that is too high is no protection at all.
Step 6: dead time and shoot-through in bridge circuits
- Dead time follows "device switching time plus driver propagation delay plus temperature and lot margin": commonly tens of nanoseconds to about 1 microsecond for low-voltage MOSFET half bridges and a few microseconds for IGBT bridges. Too short causes shoot-through; too long extends body diode conduction, raising loss and distorting the output waveform. Confirm the value by measurement.
- Body diode reverse recovery: during dead time the low-side body diode freewheels, and when the high-side device turns on the reverse recovery charge must be removed, creating a current spike and drain-source overshoot. The fixes are a larger Rg on, a shorter dead time, or paralleling a fast-recovery or Schottky device to improve the freewheel path (rectifier and reverse protection selection is covered in How to Select a Rectifier Diode (Chinese)).
- Synchronous rectification and motor drive bridges: in low-voltage BLDC drives, bridge dead time and drive parameters directly affect commutation noise and torque ripple. The overall approach is covered in How to Design a Low-Voltage BLDC Control Solution (Chinese).
Gate waveform debugging table
Start from the waveform in the field; it is far faster than swapping parts.
| Waveform symptom | Common cause | Direction |
|---|---|---|
| Large ringing or sustained oscillation on the gate | High gate loop parasitic inductance, gate resistor too small, drive return sharing a trace with the power loop | Shrink loop area, increase gate resistor, switch to a Kelvin source |
| High VDS overshoot at turn-off | Large loop inductance plus turn-off that is too fast | Increase turn-off resistor, improve layout, add clamping if needed (TVS or RC snubber) |
| Shoot-through destroying the half bridge | Miller false turn-on, insufficient dead time, asymmetric driver propagation delay | Stronger Miller suppression, larger dead time, measure the delay difference between the two devices |
| Clearly asymmetric heating between high and low side | Unequal body diode conduction during dead time, asymmetric complementary drive | Adjust dead time, check complementary drive and bootstrap supply |
| Heating rises noticeably with switching frequency | Insufficient drive capability, gate resistor too large, too long a Miller plateau dwell | Increase drive capability, reduce gate resistor, consider a lower Qg device |
Related reading
- Main path MOSFET selection and paralleling (including current sharing with an individual gate resistor per device): How to Select Charge and Discharge MOSFETs for a BMS Protection Board
- Overall low-voltage motor drive bridge design and dead time handling: How to Design a Low-Voltage BLDC Control Solution (Chinese)
- Voltage platforms and loss calculation for CR Micro IGBT, MOSFET and SiC: How to Select Power Devices for Residential Storage and Inverters (Chinese)
- Drive loop and device replacement boundaries (why SiC needs negative turn-off bias and a Miller clamp): Can a SiC MOSFET Replace an IGBT (Chinese)
- Clamping device selection for turn-off overshoot and port surge: How to Select a Low-Clamping TVS for a BMS Protection Board (Chinese)
FAQ
Q1: How do I select a MOSFET gate resistor, and what value in ohms is right?
There is no universal value. The gate resistor balances switching loss, dv/dt and gate ringing, and typical designs land between a few ohms and a few tens of ohms. The engineering method: estimate peak current from the datasheet Qg curve using Ig is approximately (drive voltage minus Miller plateau voltage) divided by (external resistor plus internal gate resistance), start from a small value, then increase while watching VGS and VDS until ringing disappears and switching loss is still acceptable. Use a diode plus resistor for asymmetric turn-on and turn-off values, with turn-off normally smaller than turn-on. The final value follows measured waveforms and temperature rise on the complete product; internal gate resistance and recommended drive conditions follow the manufacturer datasheet.
Q2: Why does a MOSFET turn on falsely, causing shoot-through, and how do I suppress the Miller effect?
When one device in a half bridge switches, the drain-source voltage of the other rises rapidly. The displacement current I = Cgd times dv/dt couples through the Miller capacitance into the gate loop and develops a voltage across the turn-off loop impedance. If it lifts the gate above the threshold, the device that should be off conducts briefly, producing shoot-through and destroying the devices. Mitigations in order of value: reduce turn-off loop impedance (smaller turn-off resistor, integrated pull-down or dedicated sink in the driver, shortest possible gate trace); negative turn-off bias (common for IGBT and SiC, to move further from the threshold); a driver IC with an active Miller clamp; or added gate-source capacitance (which slows switching and raises drive loss, suitable only for low-power slow-switching cases). Use I = Cgd times dv/dt for an order-of-magnitude estimate, but Miller capacitance varies non-linearly with drain-source voltage, so the waveform must be measured.
Q3: Why does a MOSFET drive circuit heat up, and how do I debug a hot driver IC?
Separate driver IC heating from power device heating. Driver IC heating comes mainly from gate drive power, estimated as P is approximately Qg times switching frequency times drive voltage swing: Qg of 100 nanocoulombs, 100 kilohertz and a 10 V swing gives about 0.1 W per device, multiplied across paralleled devices or higher frequency — the most common cause of a hot driver. Add the conduction loss of the internal totem pole. Power device heating is usually dominated by conduction loss (I squared times hot RDS(on)); if heating rises noticeably with switching frequency, the switching loss share is large, usually from insufficient drive capability, too large a gate resistor, too long a Miller plateau dwell, or oscillation from gate loop parasitic inductance. Debug in order: measure VGS rise and fall times and ringing, then recalculate loss from the hot RDS(on).
Q4: Can the charge and discharge MOSFETs on a BMS board be driven directly from an MCU IO pin?
Usually not recommended, for three reasons. Drive current capability: a single MCU IO typically handles tens of milliamperes, while high-current paralleled MOSFETs carry significant gate charge, so the peak and average drive current for high-frequency switching easily exceeds the pin. Insufficient level: a 3.3 V IO driving a standard (non-logic-level) MOSFET gives too low a gate-source voltage, so on-resistance is clearly above the datasheet nominal value and the device runs abnormally hot; RDS(on) must be checked under the 3.3 V condition. Missing functions: direct drive cannot provide separate turn-on and turn-off resistors, a fast pull-down or a Miller clamp. Use a dedicated gate driver IC or pre-driver. Only in low-frequency, low-current, slow-switching cases is direct drive of a logic-level MOSFET worth considering, and even then threshold voltage and the RDS(on) specification at 3.3 V must be checked against the manufacturer datasheet.
Contact us
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Disclaimer: This article is technical education and industry exchange for reference only and is not selection, procurement or other commercial decision advice. Drive voltages, gate resistor values, drive power and dead times quoted here are typical industry ranges or order-of-magnitude estimates; real values vary significantly between manufacturers and device generations. Final design must follow the recommended operating range and absolute maximum ratings in the manufacturer datasheet plus measurement on the complete product.