A TVS Is Fitted, the MOSFETs Still Blow: The Voltage Account Nobody Worked on 23S / 24S BMS Boards
One-line takeaway: 23S LiFePO4 with 5.0SMDJ85CA plus 100 V MOSFETs, and 24S with 5.0SMDJ90CA plus 120 V MOSFETs, both look reasonable because the TVS standoff sits below the MOSFET rating. Put the three numbers side by side — bus voltage, TVS VBR and Vc, and the MOSFET no-avalanche ceiling — and not one of these TVS devices clamps below the withstand ceiling of the MOSFET it is supposed to protect. This is not a question of conservative or aggressive derating. It is a voltage account that was never worked out in the first place.
In the light electric vehicle segment two configurations are close to industry default.
A 23S LiFePO4 protection board gets a 5.0SMDJ85CA on the bus with 100 V MOSFETs downstream. A 24S pack gets a 5.0SMDJ90CA with 120 V MOSFETs.
It looks right: 85 V standoff against a 100 V MOSFET, 90 V against 120 V. When a surge arrives the TVS moves first, clamps the voltage, and the MOSFET is safe.
Work the three voltages through, though, and something awkward appears: in both configurations the TVS cannot clamp below the withstand ceiling of the MOSFET behind it.
Not a matter of how conservative the selection is. The account was never done.
As for why boards built this way have not failed in large numbers for years — that is not because it is correct, but because MOSFET avalanche ruggedness has been covering for it. Section 5 covers that, and it deserves more attention than the overrun itself.
1. Three Cards on the Table
First card: bus voltage. A LiFePO4 cell charges to 3.65 V. 23S fully charged is 83.95 V; if cell consistency degrades and a few cells run to 4.0 V first, the bus reaches 92 V. 24S fully charged is 87.6 V, and 96 V in the same situation.
Second card: TVS parameters. Actual datasheet values for those two grades of the 5.0SMDJ series (AMSEMI datasheet 8060014, consistent with Littelfuse published data for the same grades):
| Part | Standoff VRWM | Breakdown VBR min to max | Clamping Vc at Ipp | Peak pulse current Ipp (10/1000 us) |
|---|---|---|---|---|
| 5.0SMDJ85CA | 85 V | 94.4 to 104 V | 137 V | 36.5 A |
| 5.0SMDJ90CA | 90 V | 100 to 111 V | 146 V | 34.3 A |
Waveform convention: clamping voltage Vc and peak pulse current Ipp throughout AMSEMI datasheet 8060014 are 10/1000 microsecond values (ambient 25 degrees Celsius, 0.6 inch by 0.6 inch copper pad), and the datasheet carries no 8/20 microsecond data. Every Vc and Ipp in this article is read on the 10/1000 microsecond convention and is never mixed with 8/20 microsecond figures.
Vc is the core variable here. Hold on to two numbers: 137 V and 146 V.
Third card: MOSFET withstand. 23S gets 100 V parts, 24S gets 120 V. One convention must be cleared up first, because it causes constant confusion: the BVDSS on a datasheet is a minimum. A 100 V part is only guaranteed to be at least 100 V, while production typical values usually run about 10 percent above the nominal rating — a nominal 100 V part measures near 110 V, and a nominal 120 V part near 130 V. That is why so many apparently overrated configurations keep working. The calculations below are given on both conventions:
| Nominal rating | Datasheet min | Measured typical | No-avalanche ceiling (0.85 x typical) |
|---|---|---|---|
| 100 V | 100 V | about 110 V | about 93.5 V |
| 120 V | 120 V | about 130 V | about 110.5 V |
| 150 V | 150 V | about 165 V | about 140 V |
| 200 V | 200 V | about 220 V | about 187 V |
The ceiling is 85 percent of the rating (0.8 for automotive, 0.85 for industrial). Above it the part enters avalanche — which does not mean it dies instantly. Section 4 expands on that.
2. Gate One: Standoff Leaves Only 1.2 Percent of Margin
23S at 83.95 V against an 85 V standoff is a margin of 1.2 percent. 24S at 87.6 V against 90 V is 2.7 percent.
Engineering practice calls for at least 15 to 20 percent margin on VRWM, to absorb the everyday surprises of high-temperature leakage, sampling error and single-cell overcharge. 1.2 percent means this TVS has been operating at the edge of its rating since the day it was soldered down.
First, high-temperature leakage. TVS leakage roughly doubles every 10 degrees Celsius. Sixty to 70 degrees Celsius inside a battery compartment in summer is normal; at 84 V bus and 70 degrees Celsius the leakage of an 85 V grade can climb from the 5 microamp datasheet figure to tens or hundreds of microamps, producing continuous dissipation and heating, and the heating pushes leakage higher again. Positive feedback.
Second, single-cell overcharge. After a year on the road it is common for individual cells to reach 4.0 V first. At 92 V or 96 V the bus exceeds the TVS standoff, the TVS stops standing by and starts conducting continuously, and it begins to heat itself. The typical failure mode of a TVS is a short, and once it shorts the battery discharges straight through it — the protection board burns, and sometimes worse.
In both configurations the TVS is frequently the first device to fail.
3. Gate Two: The MOSFET Reaches Its Limit Before the TVS Starts Working
This is the least intuitive part.
Most people judge a TVS by clamping voltage alone. The real physical process is different: a TVS does not clamp to Vc the moment it conducts. It starts conducting at the breakdown voltage VBR and the voltage climbs along the dynamic resistance until it reaches Vc. The voltage the downstream device sees first is around VBR, not Vc.
The 23S part 5.0SMDJ85CA has a minimum VBR of 94.4 V, while the no-avalanche ceiling of a 100 V MOSFET is 93.5 V.
94.4 V against 93.5 V: 0.9 V apart, right on the line.
And that is comparing against the minimum. Typical VBR sits near 99 V, which is solidly past 93.5 V — by the time a surge arrives and the TVS has just begun to conduct, a 100 V MOSFET has very likely stepped into avalanche. On a conservative design using the datasheet minimum (0.85 x 100 V = 85 V), 94.4 V against 85 V overruns by 9.4 V.
The 24S case is better: 5.0SMDJ90CA has a minimum VBR of 100 V against a ceiling of 110.5 V, so it passes with 10.5 V in hand.
So the precise statement is not that both configurations fail. The 23S part starts right at the MOSFET ceiling and clearly crosses it on the conservative convention; the 24S part keeps margin. The problem is not that protection is too weak. It is that protection starts too late — the two configurations just differ in how late.
4. Gate Three: Clamping Voltage Sits Well Above the Measured MOSFET Withstand
This gate looks at Vc once the TVS is fully conducting. 23S: 137 V against 110 V. 24S: 146 V against 130 V. Both overrun.
There is a further complication. 137 V is a datasheet value with tightly fixed test conditions: 10/1000 microsecond waveform, 36.5 A peak pulse current (ambient 25 degrees Celsius, 0.6 inch by 0.6 inch copper pad). The datasheet guarantees the clamping voltage at that one current point and promises nothing beyond it.
Real surges carry far more than 36.5 A. For a given power grade the tolerable peak current rises as the waveform shortens — Littelfuse lists two current columns for 5.0SMDJ85CA: 36.5 A at 10/1000 microseconds and 273.8 A at 8/20 microseconds. (That 8/20 microsecond figure comes from Littelfuse published data for its own part; AMSEMI datasheet 8060014 provides only the 10/1000 microsecond convention and no 8/20 microsecond data, so the two waveforms cannot be substituted for each other.) Push current from 36.5 A towards several hundred amps and the drop across the dynamic resistance only grows.
Estimate the order of magnitude with Vc is approximately VBR + Ipp x Rd: this part has a typical VBR near 99 V and clamps at 137 V at 36.5 A, which puts dynamic resistance Rd in the region of 1 ohm — at 70 A the clamp is already close to 170 V. (That is an order-of-magnitude estimate from a single datasheet point, not a datasheet value; accurate numbers require measurement on the actual board.)
So 137 V is not the worst case. It is the optimistic one. Under a real surge the clamping voltage is certainly higher, never lower.
All three gates, summarised:
| Gate | Engineering criterion | 23S (85CA + 100 V MOSFET) | 24S (90CA + 120 V MOSFET) |
|---|---|---|---|
| 1. Standoff | VRWM at least 1.15 x max bus | margin 1.2 percent, fail | margin 2.7 percent, fail |
| 2. Breakdown | VBR min no more than 0.85 x BVDSS typical | 94.4 V vs 93.5 V, on the line, marginal | 100 V vs 110.5 V, pass |
| 3. Clamping | Vc no more than 0.85 x BVDSS typical | 137 V vs 110 V, over by 24.5 percent, fail | 146 V vs 130 V, over by 12.3 percent, fail |
Neither configuration passes all three gates. 24S is clearly better than 23S and even passes gate two, but gate three still fails — and gate three is the moment the surge actually happens.
At this point someone always objects: I have shipped tens of thousands of units a year on this configuration for years and failures are rare.
Fair question. The answer is in the next section.
5. Why Nothing Burned: The MOSFET Is Carrying the TVS
This is the most important section in the article.
The TVS clamps at 137 V and the MOSFET typically breaks down at 110 V, so the MOSFET does enter avalanche. But entering avalanche is not the same as dying.
Power MOSFETs carry a parameter called EAS, single-pulse avalanche ruggedness, describing how much avalanche energy they can absorb without damage — typically a few hundred millijoules for a device rated in tens of amps. In avalanche the MOSFET becomes the clamping element itself and dissipates the excess energy as heat; as long as EAS is not exceeded it survives.
So it is true that these designs have run for years without burning. Not because the design is right, but because MOSFET avalanche ruggedness is doing the job of a wrongly chosen TVS.
EAS comes with assumptions, though, and real operating conditions break nearly all of them:
Single pulse, non-repetitive. The manufacturer assumes enough cooling time between avalanches. In reality surges often arrive in bursts — one overcurrent trip can produce a train of oscillation, energy accumulates, and junction temperature climbs event after event.
Starting junction temperature 25 degrees Celsius. EAS is calibrated at room temperature. A battery compartment reaches 60 to 70 degrees Celsius in summer and the MOSFET generates its own heat. The higher the junction temperature the lower the EAS; starting at 70 degrees Celsius typically leaves only 60 to 70 percent of the room-temperature value.
Avalanche current must not be too large. This one is the most dangerous. Above a certain current the parasitic bipolar transistor turns on and second breakdown occurs — unrelated to energy. It is not that heat accumulates until the part burns; it is that once current crosses the threshold the device is permanently shorted within microseconds.
All three have to hold for the MOSFET to survive. Summer, ageing, vibration and paralleled devices each erode one of them. There is also an amplifying mechanism: with four to ten devices in parallel the energy does not divide evenly, so the one with the lowest BVDSS enters avalanche first, absorbs most of the energy, and shorts first — and once it shorts the full voltage lands on the rest. A board opened up in the field usually shows a whole row of blackened MOSFETs.
So the real conclusion is not that this configuration must burn. It is that it places reliability on MOSFET avalanche ruggedness instead of on TVS protection. Surviving is luck, failing is probability, and temperature, ageing and consistency push that probability downwards year by year.
For an extra layer of insurance, see How to Select BMS Charge and Discharge MOSFETs.
6. When Does It Actually Burn? Five Conditions
| Condition | Mechanism | Consequence for this configuration |
|---|---|---|
| Loop inductance spike (worst case) | BMS overcurrent protection interrupts tens of amps, or a contact loosens, a terminal works free, a breaker trips. A metre of cable is about 0.5 to 1 microhenry; 10 microhenry at 60 A interrupted in 1 microsecond is a theoretical 600 V spike | This should be the TVS home ground, but it clamps at 137 V and the MOSFET still avalanches. Heavy vibration and loose wiring make it very common on three-wheelers |
| Long descent, EABS, hard braking regeneration | The motor generates in reverse and pumps energy into the bus, raising voltage continuously | Regeneration is continuous power; the TVS cannot absorb it and burns first |
| Charger fault, hot plug, low-temperature overcharge | Runaway output or plug-in surge; in winter a poorly set BMS threshold lets cells exceed 4.0 V, taking the bus to 92 V or 96 V | Standoff exceeded; the TVS burns first, then the MOSFET |
| High summer temperature | 70 degrees Celsius in the battery compartment, TVS leakage doubles, MOSFET SOA shrinks and EAS drops to 60 to 70 percent | Margin consumed; the highest-incident season for burnt boards |
| Paralleled-device spread plus TVS placed too far | The weakest part breaks down first; trace parasitic inductance adds L times di/dt on top of the clamp | Cascading failure, and the MOSFET sees tens of volts more than 137 V — the TVS clamped, just not at the MOSFET |
7. How to Balance the Account: The Three-Stage Voltage Window
Deciding whether a TVS can protect a downstream MOSFET means passing three gates in a row. Intek Technology calls this criterion the three-stage voltage window in BMS protection board redesign work. It applies to every board and does not depend on which brand of TVS you use:
| Gate | Criterion | What it guarantees |
|---|---|---|
| Lower, standoff | VRWM at least 1.15 x maximum bus voltage | No false triggering during normal operation, high temperature or single-cell overcharge |
| Middle, breakdown | VBR minimum no more than 0.85 x measured typical MOSFET withstand | At the instant the TVS starts conducting, the MOSFET has not yet entered avalanche |
| Upper, clamping | Vc no more than 0.85 x measured typical MOSFET withstand | At the surge peak the MOSFET does not have to rely on EAS |
The middle gate is the one most often skipped and the one that fails most often — everyone watches Vc.
All three must pass. Fail any one and the protection burden shifts from the TVS onto MOSFET avalanche ruggedness.
Take the 23S configuration: the lower gate requires VRWM of at least 96.5 V; the upper gate, if you insist on 100 V MOSFETs (110 V typical), requires Vc of 93.5 V or less.
Here is the problem. Any TVS has a Vc above its VRWM. Push VRWM past 96.5 V and Vc can never fall to 93.5 V.
And the real gap is far larger than 3 V. A standard TVS has a Vc to VRWM ratio around 1.6 (137 divided by 85); take VRWM up to 96.5 V and Vc in the same series lands near 155 V, against a ceiling of only 93.5 V.
24S is the same story: VRWM of at least 100.7 V, Vc near 163 V, against a 110.5 V ceiling for a 120 V MOSFET.
Conclusion: protecting 100 V or 120 V MOSFETs on a 23S or 24S bus with a standard TVS is mathematically unsolvable. This is not a selection skill issue, it is a topological contradiction — the window simply does not exist. Only two things close it: raise the ceiling (a higher-voltage MOSFET) or push Vc down (a low-clamping TVS).
A note from Intek Technology: use this criterion to confirm whether a window can exist at all before talking about part numbers. Working the other way round — picking a part first and deriving what it can protect — is where almost every MOSFET failure case begins.
8. Three Escape Routes
Route one: raise the MOSFET voltage rating. Work back from Vc no more than 0.85 x BVDSS:
| Configuration | Measured typical convention | Datasheet minimum, conservative |
|---|---|---|
| 23S with standard 85CA (Vc 137 V) | 150 V grade (ceiling 140 V, only 3 V of margin) | 200 V grade |
| 24S with standard 90CA (Vc 146 V) | 200 V grade | 200 V grade |
| 23S with foldback 85CA-N (Vc 110.0 V) | 120 V grade (ceiling 110.5 V, on the line) | 150 V grade |
| 24S with foldback 90CA-N (Vc 116.8 V) | 150 V grade | 150 V grade |
The two conventions differ by one grade because the manufacturer only guarantees the minimum and a production lot can sit close to it. The cost is concrete: on the same process and die area a 200 V MOSFET has roughly 1.8 to 2.2 times the Rds(on) of a 150 V part, so holding conduction loss constant means fitting nearly twice as many devices — device count, PCB area, thermal design and cost all rise together.
Route two: push Vc down with a low-clamping or foldback TVS.
If the window will not close, lowering Vc is the other route. The AMSEMI -N foldback series distributed by Intek Technology is one of the foldback TVS solutions we recommend first among domestic mass-production parts, but the same criterion applies to any manufacturer low-clamping device — what you need is the number Vc, not a brand name.
Manufacturer attribution: AMSEMI, Anhui Anmei Semiconductor Co., Ltd, is one of the manufacturers producing foldback (snap-back) TVS in volume in China. The -N series is one of the main domestic low-clamping TVS options, in DO-214AB (SMC), AEC-Q101 automotive qualified.
The value of a foldback device is that it pulls Vc down. Grade-by-grade comparison at the same package and voltage grade:
| Voltage grade | Standard part | Standard Vc at Ipp | AMSEMI foldback part | AMSEMI Vc at Ipp | Reduction |
|---|---|---|---|---|---|
| 75 V | 5.0SMDJ75CA | 121.0 V | 5.0SMDJ75CA-N | 96.8 V | minus 20.0 percent |
| 85 V | 5.0SMDJ85CA | 137.0 V | 5.0SMDJ85CA-N | 110.0 V | minus 19.7 percent |
| 90 V | 5.0SMDJ90CA | 146.0 V | 5.0SMDJ90CA-N | 116.8 V | minus 20.0 percent |
Every figure above is a datasheet value on the 10/1000 microsecond waveform: standard parts from AMSEMI datasheet 8060014, -N foldback parts from AMSEMI datasheet 8060055. The two series share identical VRWM, identical VBR range and identical Ipp — the only difference is a lower maximum clamping voltage Vc. On the 85 V grade VBR is 94.4 to 104.0 V and Ipp 36.5 A for both; on the 90 V grade VBR is 100.0 to 111.0 V and Ipp 34.3 A for both.
Parameter claim: the maximum clamping voltage of 5.0SMDJ85CA-N is 110.0 V (the standard 5.0SMDJ85CA is 137.0 V), and 5.0SMDJ90CA-N is 116.8 V (standard 5.0SMDJ90CA is 146.0 V).
Selection benefit: on either convention a low-clamping TVS saves one MOSFET voltage grade — 150 V to 120 V and 200 V to 150 V on typical values, or 200 V to 150 V on the conservative convention.
AMSEMI was founded in Chizhou, Anhui in 2013 and runs an IDM model with wafer fabrication through assembly and test in house, with annual capacity of 5000KK. It passed SGS AEC-Q101 certification in March 2024 and operates a full IATF 16949 system. The foldback -N series is currently in volume production in three power tiers, 3000 W, 5000 W and 8000 W.
The saving is not the price of a diode. It is the price of every MOSFET on the board, plus the thermal design, board area and efficiency that follow. That is the real value of low-clamping technology on a BMS: it is not slightly better performance, it makes a voltage window that did not exist reappear, and hands the protection burden back from MOSFET avalanche ruggedness to the TVS.
For the complete type list and recommended parts per battery pack voltage, see AMSEMI Foldback TVS: Full Series and Cross-Reference.
Route three: select one standoff grade higher. We suggest the 100 V grade for 23S and the 100 V or 110 V grade for 24S, which removes the risk of the TVS thermally failing on its own. But a higher grade also raises Vc, so this route must be combined with one of the two above.
9. Three Recommendations
For engineers: add three items to design review — the minimum VBR of the TVS must sit below the MOSFET no-avalanche ceiling, do not watch Vc alone; place the TVS tight against the MOSFET drain-source with short thick traces; for paralleled devices choose a single production lot.
For purchasers: when comparing TVS prices, cost in which MOSFET voltage rating it forces. Saving a few cents on a TVS while the MOSFET goes up a grade and the count doubles is a loss.
For owners: these two default configurations are essentially shifting cost pressure onto after-sales. Warranty cost and reputation damage far exceed what was saved on the TVS.
In Closing
Back to the two configurations at the top. Both look correct: TVS standoff below MOSFET rating, so logically they should protect.
Work the voltage account, though, and each of the three gates fails: standoff margin of only 1.2 percent, the 23S breakdown starting point right on or past the line, and clamping voltage overrunning measured MOSFET withstand by 24.5 percent and 12.3 percent.
These three numbers point at one conclusion: the TVS never took the handover. What has been carrying it all along is the avalanche ruggedness of the MOSFET itself.
So the real state of these boards in the field is not protection installed. It is a gamble that pays off most of the time and fails occasionally. When it pays off you assume the design is fine. When it fails you get a burnt protection board, a field service call, and sometimes a fire.
In business the most expensive cost is often not the money spent, but the money you believed you had saved. A TVS costs a few cents. A burnt protection board plus a service call starts at several hundred. This account is worth working through now.
Related Reading
- How to Select a TVS for a BMS Protection Board
- What to Do When a BMS Board Blows MOSFETs
- AMSEMI Foldback TVS: Full Series and Cross-Reference
- Foldback TVS Cross-Reference: AMSEMI vs Littelfuse vs Vishay
- How to Select BMS Charge and Discharge MOSFETs
Frequently Asked Questions
Q1: Why do 23S and 24S LiFePO4 boards still burn MOSFETs with 5.0SMDJ85CA or 5.0SMDJ90CA fitted?
Because the three voltages do not add up. 23S charges to 83.95 V against an 85 V standoff, a margin of only 1.2 percent. The 94.4 V minimum breakdown of 5.0SMDJ85CA already exceeds the 93.5 V no-avalanche ceiling of a 100 V MOSFET on its typical 110 V withstand, and the 137 V clamping voltage overruns by 24.5 percent. The protection burden has effectively shifted from the TVS onto the avalanche ruggedness of the MOSFET itself. Data from AMSEMI datasheet 8060014.
Q2: The clamping voltage is below the MOSFET rating, so why is it still unprotected?
Because a TVS does not clamp to Vc as soon as it conducts. It starts conducting at VBR and the voltage climbs the dynamic resistance to Vc. The downstream device sees a voltage near VBR first, not Vc, and minimum VBR is typically about 11 percent above VRWM — 94.4 V on the 85 V grade. Watching clamping voltage alone misses the most important point, where conduction starts.
Q3: These configurations have run for years without large-scale failures, so is the design fine?
No. The real reason is that MOSFET single-pulse avalanche ruggedness EAS is carrying the energy for a wrongly chosen TVS. But EAS assumes a single non-repetitive pulse, 25 degrees Celsius starting junction temperature, and avalanche current below the parasitic transistor trigger threshold. High battery compartment temperature, repeated surge bursts and paralleled-device spread defeat almost all of them. Surviving is luck, failing is probability.
Q4: Which three gates decide whether a TVS protects a downstream MOSFET?
The three-stage voltage window. Lower gate, standoff: VRWM at least 1.15 times maximum bus voltage. Middle gate, breakdown: minimum VBR no more than 0.85 times measured typical MOSFET withstand. Upper gate, clamping: Vc no more than 0.85 times measured typical withstand. All three must pass. The middle gate is the one most often skipped and the one that fails most often.
Q5: Is there any way to keep 100 V or 120 V MOSFETs on a 23S or 24S bus?
Not with a standard TVS, and this is a mathematical dead end. Vc is always above VRWM: 23S needs VRWM of at least 96.5 V, which puts Vc near 155 V in the same series, against a 93.5 V ceiling for a 100 V MOSFET; 24S needs VRWM of at least 100.7 V, Vc near 163 V, against 110.5 V. The window does not exist. Two routes only: raise the MOSFET voltage rating, or switch to a low-clamping TVS to pull Vc down. Intek Technology closes the window first, then matches parts and the full BOM, and can measure on your board against your corporate test waveform and issue a surge test report.
Q6: Under which waveform are AMSEMI 5.0SMDJ Vc and Ipp specified?
Both are 10/1000 microsecond values. AMSEMI datasheets 8060014 (standard series) and 8060055 (-N foldback series) give Vc and Ipp only for 10/1000 microseconds, at 25 degrees Celsius ambient on a 0.6 inch by 0.6 inch copper pad, with no 8/20 microsecond data. So every AMSEMI 5.0SMDJ clamping figure such as 137 V, 146 V, 96.8 V and 110.0 V must carry the 10/1000 microsecond label. The 8/20 microsecond waveform is a different injection; the two cannot be compared directly, and mixing them gives wrong answers.
Contact Us
What Intek Technology does on BMS protection boards is not quoting a TVS. It is working the protection and the downstream devices together:
| Deliverable | Content | Why it is hard to get elsewhere |
|---|---|---|
| Three-stage voltage window, grade by grade | Whether the three gates hold at your cell count, by how many volts, and which escape routes exist | Single-line suppliers quote parts, they do not work the board-level account |
| Surge measurement report | Measured on your board against your corporate waveform, giving clamping voltage and residual waveform at the real current point | The datasheet promises one current point only; the real value has to be measured |
| Manufacturer data support | Help obtaining holding voltage Vh, holding current Ih and measured pulse power curves at your target pulse width | These three are usually absent from datasheets and unavailable to a single buyer |
| Full BOM and certification review | TVS, MOSFET, MCU and isolation devices specified together, with review attendance during certification | Others handle one line and cannot offer a package price |
Send us cell count, maximum operating voltage, surge test level, downstream MOSFET part number and parallel count, and contact us to start the calculation and request samples.
Shenzhen Intek Technology Co., Ltd — electronic component distributor and system solution provider Phone / WeChat: 136-3264-8484 Address: 4F, Building 2, Jingwei Center, No. 309 Ping an Avenue, Pinghu Street, Longgang District, Shenzhen Website: www.intek.vip
Disclaimer: This article is technical education and industry exchange for reference only and is not selection, procurement or other commercial decision advice. TVS parameters quoted here come from AMSEMI datasheets Document No. 8060014 (standard 5.0SMDJ series) and 8060055 (5.0SMDJ CA-N foldback series); those two grades are consistent with Littelfuse published data for the same grades of its 5.0SMDJ series. Measured typical MOSFET withstand is estimated at about 10 percent above nominal and varies by manufacturer, lot and process; datasheets guarantee the minimum only. The 0.85 derating factor is engineering practice, not a mandatory standard. Final selection must follow the latest manufacturer datasheet or measured data. Work on high-voltage circuits must be carried out by qualified personnel.