How to Select an Isolated Gate Driver? 4A Source / 6A Sink, UVLO Level and CMTI under SiC High-dv/dt
Bottom line: the selection order for an isolated gate driver is set the drive-voltage platform first → pick the UVLO level → size drive capability by Qg and target switching time (4A source / 6A sink) → set CMTI margin by measured dv/dt → finally check isolation rating, package and secondary isolated supply. HOPERF CMT8602X is an isolated dual-channel gate driver: 4A peak source / 6A peak sink, typical propagation delay 40ns, max delay matching 5ns, min CMTI ±150kV/μs, configurable as dual-low-side / dual-high-side / half-bridge with programmable dead time, UVLO in 6V / 9V / 13V levels; for single-channel optocoupler replacement see CMT8603X. Pick the parameters reversed and the switch blows up after the swap — this article checks each item in that order. Parameters are from HOPERF official materials as typical values or range examples; follow the original datasheet.
flowchart TD
A["Confirm drive target<br/>MOS / IGBT / SiC<br/>gate voltage platform and Qg"] --> B["Pick UVLO level by platform<br/>6V / 9V / 13V<br/>align with secondary supply"]
B --> C["Size drive capability by Qg and target switching time<br/>4A peak source / 6A peak sink"]
C --> D{"Is edge dv/dt high?<br/>SiC / GaN"}
D -- "Yes" --> E["CMTI at 2~3x measured dv/dt<br/>±150kV/μs up, with layout and neg turn-off"]
D -- "No" --> F["Tens of kV/μs typical<br/>±150kV/μs margin ample"]
E --> G["Pick config form<br/>dual-low / dual-high /<br/>half-bridge + prog dead time"]
F --> G
G --> H["Check isolation rating and package<br/>3kV narrow / 5kV wide<br/>creepage per safety std"]
H --> I["Allocate secondary isolated supply<br/>decoupling and power-up sequence<br/>clearance under barrier"]First, two high-frequency questions
Q: Why must gate drive be isolated? Can't a non-isolated driver with bootstrap be used?
Low-voltage synchronous Buck, low-voltage motor drive and other common-ground systems only need a bootstrap capacitor for the high side — no isolation (supply detail in How to power the half-bridge high-side (bootstrap)?). But in energy storage, BMS, PCS and PV inversion, the drive-side ground is floating, even inside the high-voltage domain: the high-side source follows the half-bridge midpoint, and the higher the bus voltage and the faster the transition, the larger common-mode stress a non-isolated driver must withstand, and the gate loop is easily disturbed by common-mode current. An isolated driver separates the control side (low-voltage MCU) from the drive side (power domain) with an isolation barrier, so the common-mode current does not pass through the signal loop while also providing safety — which is why almost all high-voltage power stages use isolated drivers; the full list of "which positions must be isolated" is in Which positions in an energy-storage system need isolation?.
Q: After switching to an isolated driver, what is the most common reason the switch blows up?
By experience probability: wrong UVLO level (under-voltage drive pushes the switch into the linear region), drive capability not matching switching time (edges too slow, loss spikes), insufficient CMTI margin (false output switching under high dv/dt, bridge shoot-through), secondary isolated supply and decoupling not matched (voltage dip triggers repeated UVLO). None of the four is the isolator broken — parameters were not re-checked against the system. Each is broken down below by selection order.
Step 1: set the drive-voltage platform first, UVLO follows it
The isolated driver secondary output drive supply VDD can go up to ~36V (CMT8602X spec), but the actual voltage is set by the power switch: low-voltage MOS commonly use 10~12V, IGBT and SiC commonly 15~18V, 5V logic or special platforms use lower. UVLO (under-voltage lockout) must align with this platform.
| UVLO level | Fits drive-voltage platform | Typical device | Wrong-choice consequence |
|---|---|---|---|
| 6V | 5V platform / special low-voltage drive | low-voltage logic-level MOS, reused designs | on a high-voltage platform equals no protection, still outputs under voltage |
| 9V | 10~12V platform | low-voltage MOS (sync Buck, BMS main loop, motor drive) | 15V platform with 9V level: no alarm above 9V dip, under-voltage drive heats |
| 13V | 15~18V platform | IGBT, SiC MOSFET, high-voltage half-bridge | 12V platform with 13V level: any small ripple repeatedly triggers UVLO, intermittent work |
HOPERF CMT8602X offers 6V / 9V / 13V (suffix A / B / C, e.g. CMT8602B-N is 9V narrow, CMT8602C-K is 13V wide), CMT8603X opto-replacement offers 9V / 13V. The level must be checked with the secondary isolated supply steady-state voltage, ripple amplitude and power-up sequence: if the secondary supply cold-starts slowly or dips tens of volts under load, UVLO repeatedly triggers in the start window, showing as "failed start-up" / "hiccup" that looks like a loop problem.
Step 2: size drive capability by Qg and target switching time
The asymmetric "4A peak source / 6A peak sink" is intentional: source current charges the gate to raise VGS, sink current pulls the gate charge out to drop VGS; turn-off is made faster to avoid bridge shoot-through, so peak sink is usually larger than peak source.
The actual gate-loop peak current is roughly:
Ig,peak ≈ ΔVGS / (Rg,driver + Rg,ext + Rg,int)where Rg,driver is set by the driver peak-current capability (4A / 6A is the datasheet peak upper bound), Rg,ext is the external series gate resistor, Rg,int is the power-switch internal gate resistor. Reading peak current together with total gate charge Qg estimates the switching-time magnitude:
tsw ≈ Qg / Ig,avg (Ig,avg roughly half of peak, rough estimate)| Parameter view | Meaning | HOPERF CMT8602X typical | How to use in design |
|---|---|---|---|
| Peak source / sink current | instantaneous charge/discharge ability | 4A source / 6A sink | back-solve Ig,peak above, then set external Rg,ext |
| Propagation delay tpd | input-to-output transfer time | ~40ns typ | timing budget with dead time and sample delay |
| Delay matching / pulse-width distortion | inter-channel mismatch, edge-width distortion | max match 5ns, max distortion 9ns | input to half-bridge dead-time and min-pulse check |
| Min pulse width | narrowest input pulse transmitted correctly | min 50ns | sets max usable switching frequency and min duty |
Two easy traps: first, peak current is not the bigger the better — higher peak means larger gate-loop di/dt, harder ringing, gate-source overvoltage and EMI, and external Rg,ext is the trade-off between "switching speed" and "ringing" (setting method in How to design a MOSFET gate-drive circuit?); second, min pulse width 50ns means narrow pulses get swallowed — high switching frequency + tiny duty (e.g. light-load totem-pole PFC, peak-current-mode narrow spikes) must be checked against this floor, or pulses drop and output becomes unstable at light load.
Step 3: size the CMTI margin under high dv/dt
CMTI (common-mode transient immunity, kV/μs) measures whether the isolator can still transmit correctly when the ground potential across the barrier jumps fast. CMT8602X CMTI is minimum ±150kV/μs typical.
| Driven device | Edge dv/dt magnitude | ±150kV/μs margin | Extra to do |
|---|---|---|---|
| Si MOSFET (low-voltage sync rect) | few ~ tens of kV/μs | ample (several x) | ordinary layout |
| Si IGBT (line to tens of kHz) | tens of kV/μs | fairly ample | watch gate-loop area and common-mode return |
| SiC MOSFET / GaN | above 100kV/μs | compressed, check by measurement | 2~3x measured dv/dt, negative turn-off, clearance under barrier |
The rule is pick CMTI at 2~3x the whole-system measured maximum dv/dt, and verify bit errors with a high-dv/dt edge at prototype stage, not copy the IGBT-era rule of thumb. SiC scenarios usually also do: minimize the secondary drive-loop area, add a common-mode choke or ferrite bead on the common-mode coupling path, add negative gate turn-off to raise the false-turn-on threshold when needed, and decouple the driver secondary reference ground from the main power-loop return. CMTI is selection + layout + measurement done together.
Step 4: pick the config form and dead time
Each CMT8602X channel can be configured as dual-low-side, dual-high-side or half-bridge with programmable dead time — this decides whether it can directly replace an original half-bridge driver: a bridge arm needing complementary output plus dead time uses half-bridge mode; two independent low-side switches (e.g. dual Boost, two independent loads) use dual-low-side; two high-side switches (e.g. two high-side groups, high side of a common-source half-bridge) use dual-high-side. Dead time must be computed from "driver delay matching + switch switching time + power-loop parasitics"; delay matching of ~5ns means the device itself contributes little, the dead-time bulk is in the switch and loop parasitics — do not copy dead time as a fixed value.
Also CMT8602X has input noise rejection: it rejects input noise pulses shorter than 25ns, together with the 50ns min pulse width, blocking some glitches from the MCU side or long-line coupling, but not common-mode interference from the power side — that needs CMTI margin and layout. On the primary/secondary supply domains, VCCI is 3~5.5V (compatible with digital and analog controllers), and the two secondary drivers are functionally isolated, supporting up to 1500VDC operating voltage.
Step 5: check isolation rating, package and secondary isolated supply
Although an isolated driver is "functional isolation", rating and creepage must still be checked:
| Model group | Channel / package | Isolation rating | UVLO level |
|---|---|---|---|
| CMT8602A-N / B-N / C-N | dual-drive, SOIC-16 narrow | 3kV | 6V / 9V / 13V |
| CMT8602A-K / B-K / C-K | dual-drive, SOIC-14 wide | 5kV | 6V / 9V / 13V |
| CMT8603B-WF / C-WF | opto-replacement, SOW6 (also DUB8) | 5kV | 9V / 13V |
Narrow 3kV and wide 5kV are not options, they are safety constraints: projects going for safety certification (IEC 62368-1, GB 4943.1 class) determine creepage and clearance by working voltage, pollution degree and material group, and often must fix the wide-body package before talking about the rating number. How the three rating views (test value / operating isolation voltage / transient surge) divide work is in What does 5kVrms on an isolator mean (isolation rating)?.
The secondary isolated supply is the easiest part to miss on an isolated driver: every isolated driver needs an isolated supply at the corresponding potential domain, not just powering the driver chip itself — the isolated supply capacity must cover the average of the gate peak charge/discharge current (Ig,avg × switching frequency × drive loss, ranging tens to hundreds of mW), the decoupling capacitor must absorb the gate charge/discharge pulse current, and the isolated supply itself must meet the cross-barrier rating and creepage. Bootstrap for the half-bridge high side only fits common-ground non-isolated systems; isolated drivers as a whole use the isolated-supply route — the two look alike ("supply the high-side switch") but their scope is completely different. How to design the on-board isolated auxiliary supply (flyback turns ratio, RCD clamp, opto feedback loop) is in How to make an on-board auxiliary supply?.
Common pitfalls
| Pit | Phenomenon | Correct approach |
|---|---|---|
| UVLO level not matching drive platform | intermittent work, failed start-up; or under-voltage drive, switch heats | pick 6V / 9V / 13V by drive-voltage platform, check with secondary-supply ripple and power-up sequence |
| Drive capability只看 peak not Qg | slow edges, high switching loss; or too-large peak causes gate ringing | back-solve with Ig,peak≈ΔVGS/(Rg,driver+Rg,ext+Rg,int) and tsw≈Qg/Ig |
| CMTI copies IGBT-era rule | SiC system occasional bit errors, half-bridge shoot-through blows switch | CMTI at 2~3x measured dv/dt, with clearance and negative turn-off |
| Ignore min pulse width | light-load narrow pulses swallowed, unstable output | check max frequency and min duty against 50ns min pulse |
| Secondary isolated supply capacity/decoupling insufficient | gate peak current pulls secondary voltage down, UVLO repeats | estimate power by Ig,avg×fsw, decouple close, supply itself meets creepage |
| Narrow package forced on certified project | safety creepage fails, re-layout | set whole-system safety standard first, then back-solve package and rating |
Related solutions
- Full isolator family selection: How to select digital isolators?
- Isolation position planning: Which positions in an energy-storage system need isolation?
- Isolation rating dual view: What does 5kVrms on an isolator mean (isolation rating)?
- Optocoupler to digital isolator migration: Can an optocoupler be replaced directly by a digital isolator?
- Gate resistor and dead-time setting: How to design a MOSFET gate-drive circuit?
- Half-bridge high-side supply trade-off: How to power the half-bridge high-side (bootstrap)?
- Secondary isolated supply design: How to make an on-board auxiliary supply?
- Power-switch failure troubleshooting: What is MOSFET avalanche breakdown?
- Isolator and TVS division: Which positions in an energy-storage system need isolation?, How to do surge protection?
FAQ
Q1: What do 4A source / 6A sink mean on an isolated gate driver, and what if drive capability is insufficient?
Source current is the driver ability to output high and charge the power-switch gate, pulling VGS up; sink current is the ability to output low and pull the gate charge out, pulling VGS down. The two directions are intentionally asymmetric — turn-off is made faster to avoid shoot-through, so peak sink is usually larger than peak source (e.g. HOPERF CMT8602X is 4A peak source, 6A peak sink). Peak current sets how steep the switching edge is: the actual gate-loop peak current is roughly Ig≈ΔVGS/(Rg,ext+Rg,int+Rg,driver), where Rg,driver is set by the driver peak-current capability and an external gate resistor is added in series to limit current and suppress ringing. Insufficient drive typically shows as slower edges, higher switching loss and heating, and a longer Miller plateau that raises false-turn-on risk; in the extreme the switch leaves saturation and works in the linear region, burning in tens of microseconds. Whether it is enough must be calculated with the target switching time and gate charge Qg, not treated as bigger is better — higher peak means larger gate-loop di/dt and harder-to-control ringing and EMI. Concrete values follow the selected datasheet and measured waveform.
Q2: How to pick the UVLO level 6V / 9V / 13V on an isolated gate driver, and what if it is wrong?
UVLO (under-voltage lockout) is the protection that forces the output off when the secondary drive voltage is insufficient; the level must align with the power-switch drive-voltage platform. Three common levels: 6V for 5V logic or special low-voltage drive platforms, 9V for the 10~12V platforms common to low-voltage MOS, 13V for the 15~18V platforms common to IGBT / SiC. HOPERF CMT8602X offers 6V / 9V / 13V models (suffix A / B / C), CMT8603X offers 9V / 13V. The consequence of a wrong choice is direct: pick too low (e.g. 9V level on a 15V platform) and the driver still thinks power is fine when the secondary dips just above 9V, so the switch is under-voltage driven, transconductance drops, it enters the linear region and switching loss spikes even to thermal breakdown; pick too high (e.g. 13V level on a 12V platform) and any ripple triggers UVLO repeatedly, giving intermittent operation and failed start-up. The level must be checked with the secondary isolated supply steady-state voltage, ripple and power-up sequence. Concrete values follow the selected datasheet.
Q3: Why does the power switch blow up after switching to an isolated driver, and what are the common causes?
Blowing up after switching to an isolated driver is usually not the isolator itself failing, but parameters not re-checked against the system; four common cause classes. First, UVLO level not matching the drive-voltage platform, so under-voltage drive pushes the switch into the linear region with a sharp heat rise. Second, drive capability not matching the target switching time — peak source/sink current insufficient to complete gate charge/discharge in the required time, so edges slow and loss rises; or picked too large, so gate-loop ringing causes gate-source overvoltage. Third, inadequate CMTI margin: high-dv/dt switches like SiC / GaN couple common-mode transients onto the isolation barrier and the isolated-driver output false-switches, shoot-through of the half-bridge upper/lower. Fourth, the isolation-side design not kept up: insufficient secondary isolated-supply capacity or decoupling triggers false UVLO; copper or traces under the barrier destroy creepage; dead time and delay matching (inter-channel delay mismatch, pulse-width distortion) not re-computed for the new device timing. Suggested check order is layer by layer: secondary supply and UVLO → gate waveform and switching time → bridge shoot-through → CMTI bit errors. Concrete values follow the selected datasheet and whole-system measurement.
Q4: How much CMTI is enough for an isolated driver under SiC high-dv/dt?
CMTI (common-mode transient immunity) measures the isolator ability to keep transmitting the signal correctly without false switching when the ground potential across the barrier jumps very fast, in kV/μs. HOPERF isolated gate driver (CMT8602X) CMTI is minimum ±150kV/μs typical. Whether it is enough depends on the actual dv/dt of the driven switch: silicon IGBT and ordinary MOSFET edges are mostly tens of kV/μs, so ±150kV/μs has several times margin; SiC MOSFET edges can exceed 100kV/μs and the driver secondary sits right next to the switching node, compressing the margin, so CMTI should be picked at 2~3x the whole-system measured maximum dv/dt and verified with a high-dv/dt edge at prototype stage, together with layout clearance and negative-voltage turn-off. CMTI is selection + layout + measurement done together, not a single number. Concrete values follow the device datasheet and whole-system measurement.
Contact us
For isolated gate-driver selection check (UVLO level, drive capability and CMTI margin), HOPERF CMT-series sample application and optocoupler-replacement evaluation, please contact us.
Shenzhen Intek Technology Co., Ltd — electronic components distributor and system solutions provider Tel / WeChat: 136-3264-8484 Address: 4F, Building 2, Jingwei Center, No. 309 Ping'an Avenue, Pinghu Street, Longgang District, Shenzhen Website: www.intek.vip
Disclaimer: This article is technical popular-science and industry exchange content, for reference only, and does not constitute selection, procurement or other business-decision advice. The parameters of drive current, propagation delay, delay matching, min pulse width, UVLO level, CMTI, isolation rating and package of the isolated gate driver are taken from HOPERF official public materials (website product pages and datasheets) as typical values or range examples; they differ significantly by model and operating condition. The formulas for drive current, switching time and dv/dt are engineering-estimation methods; actual design must follow the selected model original datasheet, self-designed circuit calculation and whole-system measurement.