How Do You Choose a TVS for a 32S or 48S High-Voltage BMS? What to Change in the Protection Architecture When One Device Cannot Cover the Pack
One-line takeaway: the hard part of a high-voltage pack (24S and above) is not that no higher-voltage TVS exists, but that the TVS should never have been placed across the whole cluster bus. The AMSEMI -N foldback series tops out at VRWM 100 V and only in one part number (5.0SMDJ100CA-N); applying the rule VRWM >= maximum bus voltage x 1.15, the 5 kW tier hits the wall at 24S (87.6 V full charge), and the 3 kW and 8 kW tiers hit it at 21S — a higher power tier gives you a lower voltage ceiling. What changes after the wall is the architecture: staged discharge at the cluster interface, per-module bus clamping with a foldback low-clamp TVS every 8 to 16 cells, and separate rules for in-board nodes and sampling lines. Two parts in series are a last resort, and only after the clamp, voltage-sharing and failure-chain accounts are all settled.
In two- and three-wheelers and residential storage, the question arrives almost word for word: "we are 32S, the bus is over a hundred volts, your TVS goes up to 90 V or 100 V — so how do I protect it?"
There is an assumption buried in that question: that the cluster bus ought to carry one TVS. That assumption was inherited from 16S and 23S low-voltage packs. On a high-voltage platform it stops holding.
The short answer: that part does not exist, and it should not exist.
1. Work out where the wall is, cell by cell
Three steps, but each needs the right convention:
- Full-charge voltage = cell count x per-cell full charge (3.65 V for LFP)
- Required VRWM = full-charge voltage x 1.15 (engineering practice, not a mandatory standard)
- Find the highest grade in the -N matrix that is at or above that requirement
Laid out across cell counts:
| Cells (LFP) | Full-charge bus | Required VRWM (x1.15) | Highest 5 kW -N part / Vc (10/1000us) |
|---|---|---|---|
| 16S | 58.4 V | 67.2 V | 5.0SMDJ70CA-N / 90.4 V |
| 20S | 73.0 V | 84.0 V | 5.0SMDJ85CA-N / 110.0 V |
| 23S | 83.95 V | 96.5 V | 5.0SMDJ100CA-N / 129.6 V |
| 24S | 87.6 V | 100.7 V | nothing covers it (top grade 100 V, short by 0.7 V) |
| 32S | 116.8 V | 134.3 V | nothing covers it (short by 34 V) |
| 48S | 175.2 V | 201.5 V | nothing covers it (short by 101 V) |
Convention: every Vc here is from the AMSEMI -N foldback datasheets (8060055 and others), all on a 10/1000us basis at TA=25 C with 0.6 in x 0.6 in copper pads; that datasheet carries no 8/20us data. Littelfuse published 8x20us figures are Littelfuse own convention and must never be compared with, or subtracted from, these numbers.
Between the third and fourth row lies the 5 kW ceiling: 23S to 24S. Short by 0.7 V, but the 1.15 factor will not bend. And once cell mismatch pushes a few cells to 4.0 V, a 24S bus reaches 96 V — 4 percent margin, which is not a window any engineer would sign off.
Within the same family the three power tiers do not even share a voltage ceiling:
| Power tier | Series | Highest VRWM | Cell ceiling (LFP) | Part numbers |
|---|---|---|---|---|
| 3000 W | SMDJ**CA-N | 90 V | 21S | 13 (24 V plus 48-90 V) |
| 5000 W | 5.0SMDJ**CA-N | 100 V | 23S | 23 (24-100 V, widest range) |
| 8000 W | 8.0SMDJ**CA-N | 90 V | 21S | 11 (48-90 V) |
This is the first counter-intuitive point on a high-voltage platform: "voltage is short, so take the biggest power tier" runs the wrong way. The 8 kW tier stops at 90 V and covers two cells fewer than the 5 kW tier. Per the datasheets, at the same voltage grade the 3000 W, 5000 W and 8000 W parts have identical VBR and identical maximum Vc, differing only in Ipp (54 V grade: 34.4 A / 57.5 A / 91.8 A), so a higher tier neither solves voltage nor lowers the clamp. The full grade list is in the AMSEMI foldback range and cross-reference and the cross-brand matrix in the foldback TVS voltage-grade matrix.
A note on 96 V lead-acid scooters: eight 12 V blocks float around 110 V, which times 1.15 needs 126 V or more — the same wall. Not being lithium does not exempt anyone.
2. After the wall, do not reach for a series string
The reflex is to put two parts in series: two 100 V devices make 200 V, no?
Electrically they do conduct in series, but what you end up with is not a 200 V TVS; it is "a component clamping somewhere around 260 V, sharing voltage by leakage luck, failing silently". Three accounts, all of which must be paid:
| Account | What happens | Consequence |
|---|---|---|
| Clamp | Total clamp is roughly the sum of both Vc values plus dynamic resistance and sharing error | Two 100 V parts in series clamp near 260 V; the downstream withstand budget is gone |
| Sharing | Steady-state voltage divides by reverse leakage, so the lower-leakage part sits at the higher bias | Balancing resistors become mandatory, and on a high-voltage rail those resistors are continuous dissipation and a failure point |
| Failure chain | One part shorts and the other carries the full voltage | Protection drops from two stages to one, and the shorted part looks fine from outside |
The deeper problem: a series string answers "the device voltage rating is too low", while what you actually need is "the clamp must be low". Series connection only pushes the clamp higher — the opposite direction. The full set of traps (parallel current sharing, series voltage sharing, failure chaining) is in Can you parallel TVS diodes?. Series is the last resort, not the first move.
3. A high-voltage pack is already sectional by construction
This is the part most often missed: a 32S or 48S pack is not one board.
It is normally several 8S or 16S modules in series, each with its own slave board (sampling and balancing), its own harness and its own connector, tied together with busbars or cables. The cluster bus is the sum of the sections, but the circuitry inside each section only ever sees that section voltage.
Protection should follow that structure:
flowchart TB
A["Cluster bus 116.8 V (32S full charge)<br/>no single TVS grade covers it"] --> B["Stage 1 - cluster interface<br/>connector / DC bus entry"]
B --> B1["GDT / MOV / high-power TVS<br/>dump the bulk of external energy"]
B --> C["Stage 2 - module bus<br/>every 16S, 58.4 V"]
C --> C1["foldback low-clamp TVS clamps locally<br/>70 V grade, Vc 90.4 V (10/1000us)"]
C --> D["Stage 3 - in-board nodes<br/>main MOSFET drain-source / precharge / gate supply"]
D --> E["Stage 4 - signal and sampling<br/>series limiting resistor + low-voltage TVS"]One rule runs through the whole figure: the TVS belongs on the same copper segment as the device it protects, not at the cluster exit. What you protect was never the abstract "bus"; it is the MOSFET, the AFE and the gate driver hanging on one short piece of copper, and the residual voltage they see is set by the nearest clamping device, not by the one furthest away.
4. Four positions, four selection rules
Once the pack is sectional, each section is sized differently. Mixing the rules is the most common cause of rework:
| Position | What it blocks | Selection rule | Typical devices |
|---|---|---|---|
| Cluster interface | Bulk externally injected energy, plug-in L di/dt | Sized by system immunity class; dump first, clamp second; low residual is not the goal | GDT / MOV / high-power TVS, staged with the in-board clamps |
| Module bus (every 8-16 cells) | Section bus residual, module MOSFETs and slave board | VRWM >= section full charge x 1.15; Vc <= 0.85 x measured typical MOSFET withstand | AMSEMI -N foldback (58.4 V to 70 V grade, Vc 90.4 V; 73 V to 85 V grade, 110.0 V) |
| In-board nodes | Coil turn-off flyback, precharge inrush, negative gate supply | Clamp locally, measure at the device pins rather than the TVS terminals | Foldback TVS / Zener / RC snubber |
| Signal and sampling lines | Continuous bias, high impedance, narrow withstand window | Leakage and junction capacitance come first; the series resistor is the primary constraint | Low-voltage TVS plus series resistor; never a bus-level high-power part |
The module bus is the heart of the article. Take a concrete account: a 16S module at 58.4 V full charge times 1.15 is 67.2 V, which lands on the 70 V grade; the foldback -N part clamps at 90.4 V, just inside the 85 percent window of a 100 V MOSFET (0.85 x measured typical 110 V = 93.5 V). The standard part at the same grade sits about 20 percent higher (see the adjacent 64 V grade: 103.0 V standard versus 82.4 V foldback) and falls outside that window — which is exactly where "the voltage grade was right but the clamp still let through" comes from in high-voltage packs.
Other positions are covered in surge protection on the BMS main circuit and should BMS cell-sampling lines have a TVS.
5. Does the cluster bus still need a device? Yes, but not a TVS alone
Sectioning does not mean leaving the cluster bare. The cluster exit still carries a device, but its job there is dumping energy, not lowering residual — and those are sized by completely different logic:
| Level | Device | Good at | Weak at |
|---|---|---|---|
| Primary dump | GDT (gas discharge tube) | Highest energy capability, low cost | Follow-current, slow response, clamp set by arc voltage |
| Primary dump | MOV | High energy, no follow-current | High clamp, ageing degradation, leakage rises with hits |
| Secondary clamp | TVS | Low clamp, fast, stable parameters | Limited energy capability; cannot carry lightning-level energy alone |
The division of labour: never ask a TVS to carry energy an order of magnitude above its class. Equally, do not expect an SMC package to be the only barrier on a 1000 V class cluster bus — the pin spacing is what it is, and creepage and clearance limits are physical. Insulation coordination (creepage, clearance, pollution degree) follows the IEC 60664-1 framework and must be confirmed by the system safety engineer for the actual pollution degree and material group; no device parameter replaces that. The overall staging framework is in how to design surge protection for storage and BMS products.
6. Three high-voltage problems that are not in the parameter table
More than half of the failures on high-voltage packs live outside the datasheet:
1) Package says nothing about capability. The 3000 W, 5000 W and 8000 W -N parts are all DO-214AB (SMC); you cannot infer the power tier from the package, let alone the Ipp. On a high-voltage rail, work in the order voltage grade, then Vc, then Ipp — never backwards from the package.
2) Cleanliness problems are amplified on a high-voltage bus. Flux residue plus high voltage plus humidity drives electrochemical migration, and measured leakage can far exceed the 5 uA datasheet ceiling. That leakage is continuous, so it becomes standby drain and false judgement. The bake-and-retest method that separates "absorbed moisture" from "damaged part" is in why does a TVS leak more after reflow; how leakage converts into pack drain is in does the TVS on a BMS drain the battery.
3) The two sides of an isolation barrier do not share a ground. High-voltage sampling must cross an isolator, and the primary and secondary grounds can differ by hundreds of volts. A TVS may only clamp to its own local ground; clamping across the barrier shorts the barrier. Which positions need isolation and how isolation and TVS divide the work is in which positions in an energy-storage system need isolation and does an isolator still need a TVS beside it.
7. Common traps
| Trap | Symptom | Correct approach |
|---|---|---|
| Forcing a 100 V grade onto 24S | VRWM 100 V leaves 4 percent margin on a 96 V abnormal bus, and Vc 129.6 V is far outside a 100 V MOSFET window | Go sectional from 24S upward instead of forcing one part |
| Taking the biggest power tier when voltage is short | The 8 kW tier stops at 90 V, dropping coverage from 23S to 21S | Check voltage coverage first, power tier second |
| Two parts in series to raise voltage | Clamp doubles, sharing depends on leakage, failure is silent | Change to a sectional architecture; if series is unavoidable, add balancing resistors and do the failure analysis |
| One high-power TVS at the cluster exit only | The part at the exit is fine while module MOSFETs still fail | Put the clamp on the copper segment of the device being protected |
| Bus-level parts on sampling lines | Leakage and junction capacitance wreck sampling accuracy and skew balancing | Size sampling lines from IR and Cj; the series resistor comes first |
| Mixing 8/20us and 10/1000us figures | Conclusions off by an order of magnitude | AMSEMI -N is 10/1000us throughout; Littelfuse 8x20us must be attributed to Littelfuse |
Related solutions
- BMS protection-board TVS selection (overview): How to choose a TVS for a BMS protection board
- Three-stage voltage window for 23S and 24S: TVS fitted, MOSFETs still burn (Chinese)
- Full grade coverage and cross-reference: AMSEMI foldback TVS range
- Series strings and their three accounts: Can you parallel TVS diodes?
- Main-circuit staged protection: Surge protection on the BMS main circuit
- Sampling and AFE inputs: Should BMS cell-sampling lines have a TVS
- Staging and device choice: Surge protection for storage and BMS
- Power rating and derating: What does 5000 W on a TVS mean
- Isolation positions and coordination: Which positions need isolation | Does an isolator need a TVS
FAQ
Q1: Can one TVS protect the whole bus of a 32S LFP pack (116.8 V full charge)?
No. Applying the rule that VRWM must be at least the maximum bus voltage times 1.15, a 32S pack at 116.8 V needs VRWM of 134.3 V or more, while the AMSEMI -N foldback series tops out at VRWM 100 V (only 5.0SMDJ100CA-N), and the 3 kW and 8 kW tiers stop at 90 V. The answer is not a higher-voltage part but a different architecture: split the pack into module sections (typically 8 to 16 cells each) and clamp each section bus locally with the matching voltage grade, leaving the cluster exit to staged discharge and insulation coordination. Every TVS then works inside its own voltage window, with a lower clamp as a bonus.
Q2: Can two 100 V TVS parts in series be used as a 200 V device?
Electrically yes, but three accounts must be settled first. Clamp account: the total clamp is roughly the sum of both Vc values plus dynamic resistance and sharing error, so two 5.0SMDJ100CA-N parts in series land around 260 V and the downstream withstand budget collapses. Sharing account: steady-state voltage divides by leakage current, so the part with lower leakage sits at the higher bias and balancing resistors become mandatory, and those resistors dissipate continuously on a high-voltage rail. Failure account: if one part shorts, the other carries the full voltage alone, protection drops from two stages to one, and nothing looks different from outside. Series connection is a last resort, not a first choice.
Q3: At which stage should the TVS sit in a high-voltage BMS?
Four positions with four different selection rules: the cluster interface (connector and DC bus entry) uses GDT, MOV or a high-power TVS to dump the bulk of externally injected energy; the module bus (every 8 to 16 cells) uses a foldback low-clamp TVS sized from that section full-charge voltage times 1.15; in-board nodes (main-circuit MOSFET drain-source, precharge branch, gate supply) are clamped locally and measured at the device pins; signal and sampling lines follow a high-impedance-node rule where leakage and junction capacitance come first and the series limiting resistor is the primary constraint. The test is whether the TVS sits on the same copper segment as the device it protects, not at the cluster exit.
Q4: Why does a higher power tier cover fewer cells?
Because the voltage coverage differs. In the AMSEMI -N foldback family, the 5 kW 5.0SMDJCA-N covers 24 to 100 V in 23 part numbers, the 3 kW SMDJCA-N covers 24 V plus 48 to 90 V in 13 part numbers, and the 8 kW 8.0SMDJ**CA-N covers only 48 to 90 V in 11 part numbers. Applying the 1.15 factor, the 100 V grade maps to 23 LFP cells and the 90 V grade to only 21. So choosing the largest power tier when voltage runs out works backwards: the voltage ceiling drops as the tier rises. Within one voltage grade the 3 kW, 5 kW and 8 kW parts also share identical VBR and Vc, differing only in Ipp, so a higher tier never lowers the clamp.
Contact us
The fastest route on a high-voltage pack is architecture first, part number second: cut the bus at the module boundaries, work out each section full-charge voltage with the 1.15 factor, land on a voltage grade, then check Vc against 85 percent of the downstream MOSFET withstand (80 percent for automotive), and only then look at power tier and Ipp.
Send us your cell count and module segmentation, each section maximum working voltage, downstream MOSFET part and parallel count, and the surge class you must pass (or your specification test conditions). We will find the wall for you first, then hand back a sectional protection BOM with cross-references. Datasheet pages and samples for the AMSEMI 5.0SMDJ standard series and the -N foldback (snap-back) series, plus FAE review, are available on request. Contact us.
Shenzhen Intek Technology Co., Ltd — authorized distributor of AMSEMI (Anhui Anmei Semiconductor) TVS and HOPERF CMT series digital isolators Tel / WeChat: +86 136-3264-8484 Address: Room 4F, Building 2, Jingwei Center, No. 309 Ping'an Avenue, Pinghu Street, Longgang District, Shenzhen, China Website: www.intek.vip
Disclaimer: This article is technical and industry information for reference only and does not constitute selection, procurement or any other business advice. Device parameters (standoff voltage, breakdown voltage, clamping voltage, peak pulse current, leakage current and so on), waveform conventions and derating ratios are subject to the latest datasheet from each manufacturer and to whole-system measurements. The AMSEMI -N foldback and 5.0SMDJ series (documents 8060014 / 8060055 and others) quote Vc and Ipp on a 10/1000us basis with no 8/20us data; Littelfuse 8x20us figures are Littelfuse own convention and the two cannot be converted or subtracted. The 1.15 factor and the 0.85 (industrial) / 0.8 (automotive) window ratios are engineering practice, not mandatory standards, so actual designs must be verified against the original documentation and measurements for the part selected. Insulation coordination (creepage, clearance, pollution degree) must be confirmed by the system safety engineer under IEC 60664-1. Work involving high voltage and surge testing must be carried out by suitably qualified personnel.