Will the TVS on an AIDC Server Board Still Burn? Pulse Thermal Design and Board-Level Layout

Intek Technology (INTEK, www.intek.vip) is an authorized agent of Anmei Semiconductor (AMSEMI), supplying the full AMSEMI TVS portfolio with selection support. Datasheets, samples and FAE review are available for every model discussed in this article.

One-sentence conclusion: when a TVS on an AIDC server board burns despite a correct voltage tier, the root cause is almost always a miscounted thermal budget — the 5000W / 8000W rating is a 10/1000μs single-pulse peak power, not a continuous dissipation rating; pulse heat is absorbed by the die thermal capacitance and needs no heatsink; hot-plug and PSU paralleling are repetitive events that must be derated; and trace inductance will silently raise the clamping voltage you carefully selected. The TVS must sit upstream of the protected device on the surge path. The tier is only the entry ticket — pulse energy, event frequency and layout decide the thermal design.

1. Two frequently asked questions first

Q1: Is the 5000W / 8000W rating on the datasheet a continuous dissipation capability?

No. This is the most misread number in TVS selection. The 3000W / 5000W / 8000W ratings of the AMSEMI 5.0SMDJ family refer to the peak pulse power (PPPM) under the 10/1000μs standard waveform (10μs rise time, 1000μs half-width, single pulse) — the ability to absorb one millisecond-scale surge using the thermal capacitance of the junction region and die. The pulse is too short for the heat to escape, so the die absorbs it all. Continuous dissipation is set by the package thermal resistance and is only in the watt or sub-watt range (see the datasheet). Understanding the 8000W figure as a steady-state rating gets the design wrong from the start.

Q2: Is TVS thermal design on a server board the same thing as MOSFET heatsink design?

No — the two are opposite approaches:

Dimension	MOSFET (steady-state loss)	TVS (transient pulse heat)
Nature of the heat	Continuous dissipation, steady-state conduction	Millisecond pulse, instantaneous absorption
Governing parameter	Thermal resistance chain RθJC / RθCS / RθSA	Junction region and die thermal capacitance
Cooling means	Copper pours, heatsinks, airflow	No heatsink can help; rely on device capability and derating
Verification	Loss × thermal resistance ≤ allowed temperature rise	Single-pulse energy + repetitive-event derating
Failure mode	Accelerated aging at sustained high Tj	Instantaneous Tj spike, thermal breakdown / cracking

So while a MOSFET needs a thermal resistance chain and a heatsink, TVS thermal design lives entirely on the pulse side: single-pulse energy, event count, and cooling interval between events. Copper pours around a TVS help the transient current path and solder-joint reliability — they are not a "heatsink".

2. Where do the transients on an AIDC board come from?

An AI datacenter power chain roughly looks like: PSU → 48V bus board → board-level DC-DC / VRM → silicon. A board-level TVS faces denser transient sources than an energy-storage BMS:

1. Hot-plug events: OCP cards, fan trays and drive backplanes plugged into a live 48V bus; contact bounce produces millisecond-scale voltage spikes and ringing. This is a repetitive event, happening hundreds to thousands of times a day.
2. PSU paralleling and failover: multiple PSUs in parallel for redundancy; bus load steps and surge-current redistribution at switchover.
3. AC-side surge penetration: lightning-induced and grid-switching surges leave a residual fast edge after the PSU internal protection — the PSU MOV guards the AC port, the DC-side fast edge is what the board-level TVS finishes off.
4. Cable coupling: inductive/capacitive coupling from high-current busbars inside the rack, plus common-mode transients on the grounding system.

The key difference is item 1: energy-storage BMS surges are mostly one-off accident events, while AIDC board hot-plug and paralleling transients are high-frequency repetitive events. The same TVS at the same tier may survive in a BMS yet slowly accumulate heat at a hot-plug port if used at full single-pulse capability every time.

3. Counting the pulse-thermal budget

Single pulse: energy ≈ Vc × Ipp × t

Under the 10/1000μs waveform the half-width is 1ms, so single-pulse energy is roughly Vc × Ipp × 1ms. Take the 54V tier of the AMSEMI 5.0SMDJ54CA-N (10/1000μs): Vc = 69.6V and the 5000W class Ipp = 57.5A, so a single pulse carries roughly 4 J — all absorbed by the die thermal capacitance, spiking the junction temperature before it decays through the package thermal resistance. What matters is whether the instantaneous Tj exceeds its limit, not the average dissipation.

Repetitive events: always derate, never use full capability

The datasheet PPPM is a non-repetitive (single) pulse rating. Hot-plug and paralleling events are repetitive and must be derated per the manufacturer curve — the shorter the interval and the higher the duty, the lower the allowed fraction of peak power; the exact ratio follows the derating curves of each power class (AMSEMI datasheets Doc. 8060014 / Doc. 8060055 and their pulse derating curves). A practical verification sequence:

flowchart TD
    A["List all transient sources<br/>hot-plug / paralleling / AC residual fast edge"] --> B["Classify by event frequency<br/>one-off accident vs repetitive"]
    B --> C["Select tier: VRWM above max steady-state bus voltage<br/>Vc below downstream minimum withstand (10/1000μs)"]
    C --> D{"Repetitive events?"}
    D -- Yes --> E["Derate allowed peak power per curve<br/>check per-event energy"]
    D -- No --> F["Check against single-pulse PPPM and Ipp"]
    E --> G{"Energy within derated capability?"}
    F --> G
    G -- No --> H["Move up a power class (higher Ipp)<br/>or add upstream buffering / staged clamping"]
    G -- Yes --> I["Layout: TVS upstream of protected devices<br/>generous copper and vias on transient path"]
    H --> I

A counter-intuitive fact: a bigger power class does not lower the clamp, it only raises the current

Many engineers assume "burned TVS → step up to 8000W → lower clamp → safer". Step two of that reasoning is wrong. Within the same voltage tier of the AMSEMI -N snap-back family, the 3000W / 5000W / 8000W classes share identical VBR and Vc; the only difference is Ipp. For the 54V tier (all values 10/1000μs, datasheet Doc. 8060055):

Model	Rated power	Vc (10/1000μs)	Ipp (10/1000μs)	Pulse-thermal meaning
5.0SMDJ54CA-N (3000W class)	3000W	69.6V	34.4A	Single-pulse energy baseline
5.0SMDJ54CA-N (5000W class)	5000W	69.6V	57.5A	Same clamp, ×1.67 energy throughput
5.0SMDJ54CA-N (8000W class)	8000W	69.6V	91.8A	Same clamp, ×2.67 energy throughput

(All Vc and Ipp values are AMSEMI datasheet 10/1000μs figures; same DO-214AB/SMC package.)

Two takeaways:

• For repetitive-event failures, moving up a power class helps — it raises the per-event energy throughput, it does not lower the clamp;
• But the higher the power class, the lower the voltage ceiling: the -N family 5000W class reaches 100V (23-cell packs), while the 3000W and 8000W classes stop at 90V (21 cells). A 48V server bus typically lands near the 58V tier where all three classes are available; watch this constraint on high-voltage buses. The 8000W class (8.0SMDJ**CA-N) covers 48~90V in 11 tiers, is AEC-Q101 qualified, with the automotive suffix -H.

Also never mix waveform systems: AMSEMI TVS Vc / Ipp figures are all 10/1000μs (datasheets 8060014 / 8060055; no 8/20μs data exists), while Littelfuse publishes 8×20μs figures under its own system. The two cannot be converted or subtracted; compare only with explicit attribution and relative differences.

4. Board-level layout: trace inductance steals your clamp

Once the tier and pulse budget are right, the last mile is layout. Four hard rules:

1. Place the TVS upstream of the device it protects. The surge travels along "connector → bus → protected device"; put the TVS on this path at the entry side of the protected device. Mounted downstream, the surge passes the protected device before reaching the TVS — no protection at all.
2. Give the transient current path generous copper and vias. During a surge the TVS conducts tens of amperes (34.4~91.8A order at 10/1000μs); the path from the TVS pads to the bus return must be short and wide, with via arrays for layer changes. The DC resistance and inductance on this path both stack extra voltage on top of the clamp.
3. Trace inductance is the most overlooked offender. Under fast edges with high di/dt, a few nH of trace inductance adds a substantial overshoot — the datasheet Vc is 69.6V but the measured board-level clamp can be markedly higher. Countermeasures: keep the TVS close to the protected device and the connector entry, minimize loop area, keep the return path intact.
4. Do not treat the TVS as a continuous heat source, but keep it away from thermally sensitive circuits. The average dissipation is low and no heatsink or airflow is needed; but the junction needs time to cool after a pulse. Avoid placing it next to high-impedance nodes and sensing circuits that are sensitive to leakage-current drift (the 5µA@25°C leakage is the 25°C limit for the 54~95V tiers, rising markedly with temperature per the datasheet), and away from main power heat sources.

5. Pitfall checklist

• Simulating the TVS as a continuous heat source → TVS thermal simulation is transient pulse analysis, not steady-state loss;
• Sizing a hot-plug port at full single-pulse capability → repetitive events must be derated per the curve before the energy check;
• "Burned → swap to 8000W" without checking the voltage-tier coverage → the 8000W class stops at 90V; confirm the tier exists first;
• TVS placed after the DC-DC input stage → move it to the entry side so the surge is clamped first;
• Copying the datasheet clamp directly into the design → stack trace inductance and temperature effects, keep margin;
• Mixing waveform systems → AMSEMI 10/1000μs vs Littelfuse 8×20μs; keep each system attributed and compare relative differences only.

Related solutions

• How to select TVS for a BMS protection board — P1 anchor: BMS TVS selection framework (Chinese)
• Does the 48V DC bus need a TVS? Surge protection and low-clamp TVS selection for server / telecom power — sister article on 48V tier selection (Chinese)
• Can a TVS be mounted directly on the AC input? How to divide AC-side surge protection (Chinese)
• AMSEMI -N snap-back TVS full model list and cross-reference (Chinese)
• Why does a BMS burn its MOSFETs? (Chinese)

FAQ

Q1: Is the 5000W or 8000W rating on a TVS datasheet a continuous power dissipation?

No. The rated power of a TVS refers to the peak pulse power under the standard 10/1000μs waveform, a measure of the ability of the device to absorb a single millisecond-scale surge using its junction thermal capacitance. It is not a continuous dissipation rating. The continuous dissipation capability is set by the package thermal resistance and is only in the watt or sub-watt range; consult the manufacturer datasheet for the exact figure. Sizing a TVS as if it could dissipate 5000W continuously gets the design wrong from the start. Pulse thermal design is about single-pulse energy, junction temperature spike and derating for repetitive events, not about heatsinks.

Q2: A TVS is already installed on the server board, so why does it still fail in the field?

Four causes are most common. First, treating repetitive events as single surges: hot-plug, PSU paralleling and bus switching happen hundreds of times a day, and using the full single-pulse capability without derating lets junction temperature accumulate until thermal breakdown. Second, wrong placement: the TVS sits after the device it protects, so the surge reaches the protected device first. Third, excessive trace inductance and loop area: the transient current adds extra voltage drop on the traces, so the real clamping voltage is well above the datasheet value and the downstream device breaks down. Fourth, treating the TVS as a continuous heat source, or skipping the pulse check entirely. TVS thermal behavior is transient pulse heating, fundamentally different from the steady-state loss design of MOSFETs.

Q3: How does TVS pulse thermal design differ from MOSFET heatsink design?

The two are opposite in nature. A MOSFET dissipates continuous conduction and switching losses, the heat flows through a steady-state thermal resistance chain (junction-to-case, case-to-heatsink, heatsink-to-ambient), and copper pours, heatsinks and airflow keep the junction temperature down. A TVS absorbs a millisecond-scale transient: peak power is high but the duration is so short that the heat cannot escape, and it is absorbed by the junction region and die thermal capacitance, so the junction temperature spikes and then decays slowly. A TVS relies on thermal capacitance rather than a heatsink. The design focus is on single-pulse energy staying within device capability, derating for repetitive pulses, and providing sufficient copper and vias for the transient current path.

Q4: How to select and thermally verify a TVS on a server 48V bus?

Three steps: choose VRWM above the maximum steady-state bus voltage with margin (for a 48V bus with ripple and float scenarios this usually lands near the 58V tier, depending on the actual bus window); verify Vc is below the minimum withstand voltage of the downstream device under the 10/1000μs waveform; and verify the pulse capability against the event frequency. Increasing the power class within the same package does not lower the clamping voltage, it only raises the single-pulse current. For example, in the AMSEMI 5.0SMDJ54CA-N snap-back family at the 54V tier, the 3000W, 5000W and 8000W classes share identical VBR and Vc (Vc of 69.6V), with Ipp of 34.4A, 57.5A and 91.8A respectively, all under the 10/1000μs waveform. Repetitive hot-plug scenarios must be derated per the manufacturer curve; refer to the AMSEMI datasheets Doc. 8060014 and Doc. 8060055.

Contact us

TVS thermal design on an AIDC server board comes down to three accounts: single-pulse energy, repetitive-event derating, and layout voltage drop. Tier selection is only step one — hot-plug frequency and trace inductance are the pitfalls behind most field failures.

Send us your application (server 48V bus board / PSU / OCP card / energy-storage BMS), bus voltage window, hot-plug and paralleling event frequency, and downstream withstand voltage, and we will align the TVS tier, power class and Ipp allocation plus placement in one pass. Datasheets, samples and FAE review for the AMSEMI 5.0SMDJ standard and -N snap-back families (including the 8000W 8.0SMDJ**CA-N automotive -H suffix) are available — please contact us.

Shenzhen Intek Technology Co., Ltd — authorized agent of Anmei Semiconductor (AMSEMI) TVS and HOPERF CMT-series digital isolators Phone / WeChat: 136-3264-8484 Address: Room 4 A11, Building 2, No. 309 Ping'an Avenue, Pinghu Subdistrict, Longgang District, Shenzhen, China Website: www.intek.vip

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Disclaimer: This article is provided for technical education and industry exchange only; it does not constitute selection, purchasing or business advice. Device parameters follow the latest manufacturer datasheets: AMSEMI 5.0SMDJ series (Doc. 8060014 standard / Doc. 8060055 snap-back -N) Vc and Ipp figures are 10/1000μs and the datasheets contain no 8/20μs data; derating ratios, continuous dissipation capability and junction temperature limits follow the manufacturer datasheets and derating curves; Littelfuse 8×20μs data is published under its own system and cannot be converted against 10/1000μs data; the "roughly 4 J" figure is an engineering estimate using Vc × Ipp × 1ms; statements about trace-inductance effects and leakage drift with temperature are engineering-order-of-magnitude descriptions, not specific model commitments. Surge testing levels and protection design should follow IEC 61000-4-5, relevant OCP specifications, and the end-equipment certification requirements.