Does a USB-C PD Port Need Isolation? Isolation Positions, VBUS Grading and TVS Protection
Intek Technology (INTEK, www.intek.vip) is an authorized distributor of AMSEMI (Anhui Anmei Semiconductor Co., Ltd) and of HOPERF CMT digital isolators, responsible for supply and selection support across both lines. For any model, parameter or selection point discussed here, we can provide datasheets, samples and FAE review against your actual operating conditions.
Bottom line: most USB-C PD ports do not need their own isolation. There is only one test — is the port ground the same node as the controller ground? If it is (the PD output of a portable power station or power bank, or the in-unit PD output of an all-in-one machine, all sitting on the battery side), skip signal isolation and put the isolation where it belongs: in the AC-DC stage, where the main transformer carries reinforced insulation and the feedback and communication channels use an isolated amplifier or digital isolator as needed. Only when the port and the controller sit at different grounds (port on the isolated side, dual-MCU architecture) do you isolate the I2C or UART. But isolation and TVS are two independent decisions: whatever you decide about isolation, the TVS stays, and one part cannot cover all three pins — VBUS is an energy problem, CC and D+/D- are signal-integrity problems, GND is a return-path problem, three parameter sets. The classic mistake is putting a 48 V grade TVS across a 48 V EPR rail: the 50.4 V steady-state ceiling already exceeds its standoff, so the part heats until it shorts. HOPERF CMT figures below follow official material as typical values or grades; confirm against the original datasheet.
flowchart TD
A["Designing a USB-C PD port<br/>ask two independent questions"] --> B{"Is the port ground the same<br/>node as controller / battery ground?"}
B -- "Same ground<br/>power station / power bank / all-in-one" --> C["No signal isolation<br/>isolate in the AC-DC stage"]
B -- "Different grounds<br/>port on isolated side / dual MCU" --> D["Isolate I2C or UART<br/>CMT digital isolator"]
C --> E{"What is the maximum<br/>steady-state VBUS?"}
D --> E
E -- "20 V SPR<br/>21.0 V peak" --> F["24 V grade<br/>Vc 31.1 V"]
E -- "28 V / 36 V EPR" --> G["36 V / 45 V grade<br/>Vc 46.4 V / 58.1 V"]
E -- "48 V EPR<br/>50.4 V peak" --> H["58 V grade<br/>Vc 74.8 V"]
F --> I["Check the window: Vc <= 0.85 x downstream rating<br/>otherwise raise the rating or stage it"]
G --> I
H --> I
I --> J["CC / D+ / D- get low-capacitance parts<br/>never shared with VBUS"]
J --> K["Bench: inject at the connector pins<br/>probe the downstream pins, not the TVS"]1. Decide one thing first: is the port ground the same node as the controller?
The isolation question gets asked far more often than it is actually needed. The reason is simple: a USB-C port is a low-voltage DC port, and in most products it lives next to the battery. Reduce the decision to a table:
| Product architecture | Where the PD port sits | Isolate this port? | What actually matters |
|---|---|---|---|
| External PD adapter plus DC input | Isolation inside the adapter (primary to secondary); the device side shares ground with the port | No | Adapter meets reinforced insulation; device DC input gets a bus TVS |
| All-in-one (AC-DC + inverter + PD output) | PD port on the battery / DC side | No, unless the PD controller is fed from the high-voltage side | Isolation in the internal AC-DC stage; staged VBUS TVS |
| Port and controller at different grounds (port on the isolated communication or sensing ground, dual MCU) | Other side of the barrier | Yes | Isolated I2C or UART; separate TVS on each side |
The rule is one line: look at the ground, not the voltage. Same ground — an isolator buys nothing and adds a common-mode false-switching risk. Different grounds — skipping it bets communication reliability on luck. What actually determines whether the port survives is always the energy path, not the isolation.
The third row deserves a note. It appears on high-string-count BMS and PCS designs as an "isolated-side user port": the PD controller follows the isolated MCU and its ground is not the main ground. There, direction handling and pull-up value selection on the isolated I2C are more error-prone than choosing the isolator itself; see Isolating I2C Sensors on the High-Voltage Side.
2. When isolation is needed, there are four positions in a charging system
Isolation is not one component. In a charger with an AC-DC stage, four channels cross the barrier, and they are quite different in nature:
| Position | What crosses the barrier | Device used | Key specification |
|---|---|---|---|
| Main power transformer | Energy plus reinforced insulation | The transformer itself | Creepage, clearance, equipment safety class |
| Feedback channel | Output voltage / current error signal | Classic TL431 plus optocoupler; newer: isolated amplifier or isolated sigma-delta plus digital isolator | Accuracy, loop bandwidth, CMTI, power-up default |
| Protocol / comms channel | PD controller to host MCU over I2C or UART | Isolated I2C, general digital isolator (CMT812X / 804X class) | Direction handling, pull-up value, rate and delay |
| Synchronous rectification / gate drive | Primary-side controller driving a secondary-side FET | Isolated gate driver (CMT8602X / 8603X class) | Propagation delay, CMTI, UVLO, default output |
The first row is a safety-standard problem, not a selection problem. No digital isolator replaces the transformer: its withstand voltage may be high, but it transfers no power, and power isolation only comes from a transformer with adequate creepage and clearance. Most boards where "the isolation was done but accomplished nothing" fail exactly here, in the mechanical and layout side, not in the part number — see Isolation Barrier PCB Layout and Isolated Supply.
The other three rows are selection problems, and they share two habits worth adopting early. First, use the minimum CMTI, not the typical figure (the typical value holds at 25 °C and a specific swing; the worst case is maximum temperature plus maximum rate plus maximum common-mode swing). Second, decide the default output level first — at power-up the input side cannot be trusted, and the wrong default pushes the whole unit into a false action; enable, alarm and interlock paths must default to "do nothing".
3. The isolator blocks common mode, the TVS absorbs energy
Field failures at a charging port or an isolated interface all look like "the link dropped" or "the port died", but three root causes exist and they belong to different parts:
| Failure path | Field symptom | Device damaged? | Owner |
|---|---|---|---|
| Common-mode false switching | Error bursts, repeated PD renegotiation, occasional misfire that clears when cool | No | CMTI margin plus layout and common-mode return |
| Surge energy injection | Burnt pins, punched barrier, dead port; sometimes the TVS is still intact | Yes | Interface TVS outside the isolator at the connector |
| Long-term field stress | Sudden barrier breakdown after two or three years, all parameters normal until then | Yes | Working-voltage derating; the TVS only reduces cumulative stress |
In one line: CMTI keeps it from misfiring, the TVS keeps it from being destroyed, derating keeps it alive. None substitutes for another: a 150 kV/us CMTI dissipates no joules, an 8 kV isolation withstand does not stop cumulative surge, and the best TVS does not slow a common-mode step.
4. VBUS grading: the four PD 3.1 voltage classes
This is the most practical part of the article. VBUS selection is three steps: find the maximum steady-state voltage, multiply by 1.15 to 1.2 to get the VRWM floor, then pick the nearest grade and check the clamp window.
USB PD 3.1 fixed voltages come in two ranges: SPR (5 V / 9 V / 15 V / 20 V) and EPR (28 V / 36 V / 48 V, up to 5 A). Use the upper edge of the plus or minus 5 percent VBUS tolerance:
| PD class | Max steady VBUS | VRWM floor (x1.15) | AMSEMI -N grade | Vc / Ipp at that grade (10/1000 us) |
|---|---|---|---|---|
| 20 V (top of SPR) | 21.0 V | 24.2 V | 5.0SMDJ24CA-N | 31.1 V / 129.0 A |
| 28 V (EPR) | 29.4 V | 33.8 V | 5.0SMDJ36CA-N | 46.4 V / 86.1 A |
| 36 V (EPR) | 37.8 V | 43.5 V | 5.0SMDJ45CA-N | 58.1 V / 68.8 A |
| 48 V (EPR) | 50.4 V | 58.0 V | 5.0SMDJ58CA-N | 74.8 V / 53.5 A |
All Vc and Ipp values are on the 10/1000 us convention (AMSEMI datasheets 8060014 standard, 8060055 foldback -N), which contain no 8/20 us data. At the same grade the foldback version clamps about 20 percent lower: 93.6 V down to 74.8 V at the 58 V grade, 103.0 V down to 82.4 V at 64 V. That 20 percent is worth a lot at a charging port, for the reason in the next section.
One reverse move to call out explicitly: do not put the 48 V grade (5.0SMDJ48CA-N, VRWM 48 V) across a 48 V EPR rail. Its standoff is below the 50.4 V steady-state ceiling, so the part stays in breakdown conduction, showing up as higher standby current and a hot TVS, then a short — while a standalone VBR measurement still looks fine. These cases get misjudged as "unstable component quality" more often than any other. Always derive the grade from the maximum steady-state voltage, never from the nominal figure. The same rule governs 48 V DC buses; see Does a 48V DC Bus Need a TVS?.
5. The window conflict at 48 V EPR, and three ways out
Grading is only step one; step two is boxing Vc into the downstream window. For 48 V EPR:
The 58 V grade clamps at 74.8 V, and with Vc <= 0.85 x downstream rating the downstream needs at least 88 V, meaning only 100 V class parts fit. But many EPR designs pick 60 V class for the VBUS switch and the DC-DC input (74.8 / 60 = 1.25, 25 percent over the window). Only three routes exist:
| Route | What to do | Cost | When it fits |
|---|---|---|---|
| Raise the downstream rating | VBUS switch, DC-DC input capacitor and switching device at 100 V class | Slightly more cost and conduction loss | Default for new designs, safest |
| Stage the protection | Large-energy low-clamping TVS at the connector plus decoupling, then a fine low-energy clamp after the VBUS switch | One extra part and a decoupling trace | Downstream already fixed and cannot change rating |
| Narrow the protection boundary | TVS covers ESD and medium surge only; bulk energy handled by the AC-side GDT/MOV or system SPD | Test level must be written down explicitly | Products with a defined staged architecture |
All three routes share one precondition: the TVS sits right at the USB-C connector. Mounted far away, the surge runs across the board first, and trace inductance times di/dt raises the residual the downstream actually sees — the datasheet Vc is the voltage across the device, excluding that trace.
6. CC and D+/D-: three constraints nothing like VBUS
VBUS is an energy problem; CC and the data lines are signal-integrity problems. On the same port the two families differ by two orders of magnitude:
| Pin | Voltage convention | Key constraint | Selection note |
|---|---|---|---|
| VBUS | 5 to 48 V, energy type | Vc below downstream rating, Ipp matched to surge level | SMB / SMC high-power, foldback to lower Vc |
| CC1 / CC2 | Absolute maximum commonly in the 5.5 V region (confirm in the port controller datasheet) | Clamp clearly below that rating and must not damage the BMC amplitude | Dedicated low-capacitance ESD array, capacitance in the low picofarads |
| D+ / D- | USB 2.0 HS 480 Mbps | Junction capacitance sets the eye diagram and error rate | Capacitance in the 0.5 to 1 pF region |
| GND / shell | Return path | Short TVS ground return, separate shield discharge path | Never route the TVS ground to the far side of the board |
The typical CC failure is not damage but "it charges, but never enters fast charging": 5 V only, negotiation timeout, reconnecting after each insertion. Almost always the CC protection device is eating the signal — too much capacitance, too much leakage, or a clamp so close to 5.5 V that the amplitude is clipped. In the field this gets blamed on an incompatible controller or a bad cable, and neither swap fixes it.
Hence a hard rule: do not share one multi-channel part between VBUS and CC / data lines. Vendor "PD port protection arrays" look convenient, but the VBUS channel and the CC channels differ by more than an order of magnitude in energy, so the part usually sacrifices one for the other.
7. How to test: where to hit, where to probe, what to judge
- Where to hit: inject at the USB-C connector pins, not at an internal node. Injecting inside removes the trace from the connector to the TVS from the test, which is exactly where the most common failure lives.
- In which state: at full negotiated load (VBUS at its actual class, 20 V or 48 V). Results taken at the 5 V default are meaningless: energy path, downstream operating point and protection bias all differ.
- Where to probe: the downstream device pins (controller supply and VBUS sense, VBUS switch drain-source, DC-DC input), not across the TVS. Across the TVS you always measure "the device clamped nicely" while the downstream is already over its rating. The full version is in How to Verify the TVS on a BMS Protection Board.
- What to judge: three layers — (1) clamp: residual at the downstream pins <= 0.85 x that device rating (about 0.8 for automotive); (2) survival: downstream undamaged; (3) protocol recovery: PD renegotiates to the original class afterwards. The third is the one most often skipped, and it is specific to charging ports — plenty of failures show up not as "will not charge" but as "charges slowly only".
- Re-measure afterwards: CC leakage, D+/D- capacitance, VBUS leakage. Degraded parameters with working function is the easiest hidden damage to miss.
ESD and surge differ by orders of magnitude in energy; never infer a surge pass from an ESD pass. Typical equipment ESD levels are 8 kV contact and 15 kV air; DC-port surge follows the IEC 61000-4-5 combination wave, with the level set by the product specification and customer requirement.
8. Common pitfalls
| Symptom | Real cause | Fix |
|---|---|---|
| TVS on a 48 V EPR port runs hot at idle, shorts months later | 48 V grade selected; the 50.4 V steady state exceeds standoff, so it conducts continuously | Re-grade from max steady voltage x1.15 to 1.2 (58 V grade) |
| Charges but never fast-charges, reconnects repeatedly | CC protection capacitance or leakage clips the BMC amplitude | Dedicated low-capacitance array on CC, clamp designed to the 5.5 V convention |
| USB 2.0 drops out, elevated error rate | Too much capacitance on D+/D- | Move to 0.5 to 1 pF class, measure before swapping |
| TVS intact, downstream device burnt | TVS too far from the connector; trace inductance raises the residual | Move the TVS next to the connector, widen the transient path with copper and vias |
| Port still destroyed with an isolator fitted | The isolator blocks common mode but dissipates no energy, and it may sit inside | Move the TVS outside the isolator at the connector |
| ESD passed, so surge is assumed to pass | The two tests differ by orders of magnitude in energy | Run both; surge per IEC 61000-4-5 |
Further reading
- The charging port as a special case of bus protection: What Is a TVS?
- Deriving the clamping window: How to Choose a TVS for a BMS Protection Board
- Dropping Vc 20 percent at the same grade: AMSEMI -N Foldback TVS Series
- The grading rule on a 48 V bus: Does a 48V DC Bus Need a TVS?
- AC side versus DC side division of labour: Can a TVS Sit Directly on an AC Input?
- Two-stage coordination at an isolated interface: Do You Still Need a TVS Next to an Isolator?
- Routing an isolated I2C: Isolating I2C Sensors on the High-Voltage Side
- Power-up sequencing and default states: Is a Digital Isolator's Default Output High or Low?
- Bench method and pass criteria: How to Verify the TVS on a BMS Protection Board
- Why a damaged port can take the MOSFETs with it: Why Does a BMS Burn Its MOSFETs? (Chinese)
FAQ
Q1: Does a USB-C PD port need isolation at all?
There is only one test: is the port ground the same node as the controller and battery ground? If it is, no signal isolation is needed for that port. The PD output of a portable power station or power bank, and the in-unit PD output of an all-in-one machine, all sit on the battery or low-voltage DC side and are already common-ground; the isolation that matters belongs to the AC-DC stage, where the main transformer provides reinforced insulation and the feedback and communication channels use an isolated amplifier or digital isolator as required. Only when the port and the controller sit at different grounds (PD controller on the isolated communication or sensing ground, dual-MCU architecture with separately supplied sides) do you need to isolate the I2C or UART. Note that isolation and TVS are two independent decisions: where no isolation is needed the TVS is still mandatory.
Q2: For a PD 3.1 48 V EPR port, which grade should the VBUS TVS use, and why not the 48 V grade?
Derive the grade from the maximum steady-state bus voltage times 1.15 to 1.2, never from the nominal figure. A 48 V EPR rail with a plus or minus 5 percent tolerance peaks near 50.4 V, and 50.4 times 1.15 is 58 V, so the 58 V grade applies (AMSEMI 5.0SMDJ58CA-N, VBR 64.4 to 71.2 V, Vc 74.8 V, Ipp 53.5 A at 10/1000 us). The 48 V grade (5.0SMDJ48CA-N, VRWM 48 V) stands below the 50.4 V steady-state ceiling, so the part sits permanently in breakdown conduction and shows up as standby leakage, self-heating and finally a short, which is easily misdiagnosed as a bad component. At the same grade the standard 5.0SMDJ58CA clamps at 93.6 V versus 74.8 V for the foldback version, roughly 20 percent lower.
Q3: The port charges but never negotiates fast charging and keeps reconnecting. Is the PD controller at fault?
Check the CC-line protection first, not the controller. CC1 and CC2 carry a BMC amplitude-modulated signal, and the controller reads levels and pulses on CC to identify the counterpart capability. If the protection device on CC has too much junction capacitance, too much leakage, or a clamp voltage close to the CC pin absolute maximum (commonly in the 5.5 V region, confirm in the port controller datasheet), the signal amplitude is eaten and the port falls back to 5 V, times out during negotiation, or reconnects repeatedly after each insertion. Use a dedicated low-capacitance ESD array on CC with capacitance in the low picofarad range and a clamp clearly below 5.5 V, and design that clamp against the CC convention rather than sharing one high-power part with VBUS.
Q4: With a digital isolator fitted, why does the PD port still get destroyed by surge?
Because the isolator and the TVS do different jobs and cannot substitute for each other. The isolator breaks the ground loop and blocks common-mode transients (a CMTI figure), but it dissipates no energy: surge can still cross the interface and burn a pin or punch through the barrier. The TVS must therefore sit outside the isolator at the connector, so the energy is diverted before it reaches the barrier; placed inside, the surge crosses the barrier first and the protection accomplishes nothing. Conversely the TVS does not stop common-mode false switching, which is a CMTI and layout problem. The mnemonic: CMTI keeps it from misfiring, the TVS keeps it from being destroyed, and working-voltage derating keeps it alive.
Contact us
Charging-port protection comes down to an energy account: the maximum steady-state voltage at the port, the surge level it must survive, the downstream device ratings, and how long each trace runs. Line up those four numbers and the grade and window almost choose themselves. The hard part is not the arithmetic — it is separating "does it need isolation" from "does it need a TVS". Most boards we see are over-engineered on isolation and mis-parameterised on protection.
Send us your PD port maximum power and voltage classes (including whether 48 V EPR applies), the ratings of the VBUS switch and DC-DC input, the trace length from the USB-C connector to the TVS, and the ESD / surge levels the product must pass. We will review the VRWM grade, the Vc window, the staging positions and the CC and data-line device conventions together. Datasheets, samples and FAE support for HOPERF CMT digital isolators and AMSEMI 5.0SMDJ / -N foldback TVS diodes are available through contact us.
Shenzhen Intek Technology Co., Ltd - authorised distributor of AMSEMI protection devices and HOPERF CMT digital isolators Tel / WeChat: +86 136-3264-8484 Address: Room 4 A11, Building 2, No. 309 Ping'an Avenue, Pinghu Street, Longgang District, Shenzhen, China Website: www.intek.vip
Disclaimer: This article is provided for technical exchange and selection reference only. It is not design, procurement or commercial advice. USB PD 3.1 voltage classes and tolerances, and the CC pin absolute maximum rating, follow the latest USB-IF specification and the datasheet of the selected port or protocol controller; the rules "maximum steady-state voltage times 1.15 to 1.2" and "Vc <= 0.85 x downstream rating (about 0.8 for automotive)" are engineering conventions, not mandatory clauses of any standard. AMSEMI 5.0SMDJ series (datasheets 8060014 standard / 8060055 foldback -N) quote Vc and Ipp at 10/1000 us and contain no 8/20 us data; Littelfuse 8x20 us figures follow that supplier own published convention and cannot be converted to or subtracted from the other waveform. Channel count, data rate, isolation class, default output state and drive strength of the HOPERF CMT family (CMT812X / 804X / 826X, CMT8602X / 8603X and others) follow the latest original datasheet; no quantified parameters are given for specific part numbers here. Work on high-voltage and battery systems should be carried out by qualified personnel.