Surge Arrives: Does the TVS Act First or the MOSFET Switch Off First? Coordinating Protection Timing in a BMS
Intek Technology (INTEK, www.intek.vip) is an authorized distributor of AMSEMI. Datasheets, samples and FAE review are available for every standard and foldback -N 5.0SMDJ part referenced below.
One-sentence conclusion: the TVS acts within nanoseconds, the MOSFETs switch off in hundreds of microseconds to milliseconds - not rivals, but a division of labour. The TVS owns the instant before protection lands and the single transient: avalanche clamping holds the voltage near Vc from the moment the surge arrives, the pulse energy is dissipated locally, and the system never loses power. The MOSFETs own the persistent anomaly: when overvoltage or overcurrent stays, the software chain samples, judges, blanks and then trips, cutting the energy source at its root. Coordination means keeping the two actions apart on both the time axis and the voltage axis: overvoltage threshold above Vc, blanking delay that filters single transients, Ipp checked against the window before turn-off lands, and a bus TVS as backstop for the turn-off flyback. Get all four right and each part does its own job; miss one and the surge lab shows you either "the board trips every time the surge fires" or "the MOSFETs die before protection moves" - two symptoms that look contradictory and share one root.
sequenceDiagram
participant S as Surge or anomaly
participant T as TVS
participant A as BMS software chain
participant M as Charge/discharge MOSFETs
S->>T: t=0 transient arrives (nanoseconds)
T-->>T: avalanche clamp holds voltage near Vc
alt single transient, energy within withstand
T-->>A: voltage falls back, event over
A-->>A: judged a transient inside the blanking window, no action
Note over A,M: system stays powered, TVS recovers
else anomaly persists
A->>A: sample, judge, blank (hundreds of microseconds to milliseconds)
A->>M: issue turn-off command
M-->>S: block both directions, energy source cut
Note over T,M: turn-off L·di/dt flyback<br/>clamped by the bus TVS
end1. Set the clocks right: three time scales
Before asking who acts first, set the clocks. A protection board has three acting parties on entirely different time scales. They face different anomalies and cannot substitute for one another:
| Acting party | Response / withstand (engineering order-of-magnitude) | What it faces | What it does |
|---|---|---|---|
| TVS avalanche clamp | nanosecond class | voltage transients (surge, ESD, flyback) | holds voltage near Vc, absorbs pulse current |
| Hardware short-circuit protection | microsecond to ten-microsecond class | hard bus short | comparator trips directly, never waits for software |
| AFE software chain | hundreds of microseconds to milliseconds | sustained overvoltage, overcurrent, undervoltage | sample, judge, blank, trip |
Put the three numbers side by side and the division of labour is clear: a single transient (a 10/1000us waveform lasts about one millisecond) is on the scale of one sampling period, so the software chain can neither react in time nor should it react - the transient belongs to the TVS, clamped in nanoseconds, dissipated locally, unnoticed by the system. Sustained anomalies belong to the software chain, because a TVS can absorb but cannot interrupt: pour a sustained overvoltage into a TVS and you drive it toward overload failure (the failure mode and its consequences are analysed in Does a TVS Fail Short or Open?). A hard bus short rises faster than any software chain, so it takes microsecond-class hardware protection or a fuse.
A large share of "we added a TVS and the board got less reliable" cases have their root in this table being set up wrong: asking the software to chase transients, or asking the TVS to hold sustained anomalies.
2. The anomaly assignment table: who owns what
| Anomaly | Who acts | Why |
|---|---|---|
| ESD, single surge pulse | TVS clamps | arrives in nanoseconds; the software can neither react in time nor should it; voltage falls back, system stays powered |
| Sustained overvoltage (charger fault, balancing runaway) | MOSFETs trip | a TVS absorbs energy but cannot interrupt it; a sustained source must be cut |
| Hard bus short | hardware short-circuit protection + fuse | MOSFET short-circuit withstand is ten-microsecond class; the software chain is far too slow |
| Inductive flyback at MOSFET turn-off | bus TVS | the faster the turn-off, the larger the L·di/dt; a clamp backstop is mandatory |
The last row is the one most often missed: the turn-off action itself creates a new transient. Opening an inductive path makes the bus and harness inductance deliver an L·di/dt spike; with no bus TVS as backstop, the MOSFETs carry it on their avalanche capability - which is how they are pushed toward avalanche failure (mechanism in MOSFET Avalanche Breakdown). Where each device belongs on the main circuit is laid out position by position in Surge Protection on the BMS Main Circuit and Suppressing Inductive Load Turn-Off Spikes.
3. Four coordination rules
Rule one: the overvoltage threshold must sit above Vc - three bands on the voltage axis
This is the root of the false-trip problem. Take a 13S NCM pack (full charge about 54.6 V): graded by VRWM at full-charge voltage x 1.15 it lands on the 64 V grade. The foldback 5.0SMDJ64CA-N clamps at Vc = 82.4 V (10/1000us convention); the standard part in the same grade is about 103 V. The overvoltage threshold must sit above 82.4 V with margin (say 86 to 88 V) while staying inside the downstream MOSFET safety window - 100 V platform MOSFETs typically break down about 10% above the label (around 110 V), and working back from Vc no more than 0.85 x measured typical breakdown, the TVS grade and the MOSFET platform are a matched pair (the window method in BMS Protection Board TVS Selection and The 23S/24S Voltage Account).
That leaves three clear bands on the voltage axis: normal operation (around 54.6 V) → TVS clamp band (82.4 V) → BMS trip band (86 to 88 V). When the TVS clamps, the bus sits at 82.4 V and never reaches the trip threshold, so the software never misjudges; if the voltage stays pinned above 82.4 V, the anomaly is persistent and the software trips on schedule.
Set the threshold at 80 V - below Vc - and every normal clamp becomes an overvoltage fault: surge tests, load steps, motor flyback, all of them trip the board. In the lab it looks like "fine all day, trips on every surge pulse", and teams blame the TVS - but the TVS did its job exactly right; the threshold turned its normal action into a fault.
Rule two: blanking delay filters single transients
Blanking (filter delay) gives the software a look-before-you-leap window: a 10/1000us pulse arrives, clamps and falls back in about a millisecond, so the blanking time should exceed the longest expected transient and let single events end inside the window. The cost is protection speed - a longer blank means the TVS carries alone for longer, which leads straight into rule three.
Rule three: check Ipp against the window before turn-off lands, not against a single datasheet point
During a surge the TVS carries alone. For how long? For the total protection delay: sampling period plus blanking plus gate turn-off. The check is to integrate the energy fed into the TVS over that window and compare it against the single-pulse Ipp and the derating curve for that pulse width (the PPPM convention in What Does the 5000W on a TVS Mean?). Blanking and TVS withstand are a seesaw: more blanking means fewer false trips but thinner TVS margin. Leave margin on both sides and close it out on the bench - injected waveform, actual MOSFET-terminal voltage, TVS temperature rise and leakage drift, with pass criteria in Bench Validation of BMS TVS Surge Testing.
Rule four: the turn-off flyback must have a backstop
The crisper the software turn-off, the larger the L·di/dt at the instant of opening. The new transient that the turn-off itself creates must be clamped by a bus TVS (or clamp network), not carried by the avalanche capability of the MOSFETs. The last step of timing design is therefore verifying the turn-off waveform: capture the bus voltage at the instant the MOSFETs open and confirm the spike stays inside the safety window, instead of only validating surge in the conducting state.
4. Common pitfalls
- Using a TVS as overcurrent protection. A TVS is a voltage-clamping device and takes almost no part in the current path; shorts and sustained overcurrent belong to hardware short-circuit protection, the fuse and the software. The time scales are one to two orders of magnitude apart - mixing them fails.
- Overvoltage threshold at or below Vc. Every normal clamp becomes an overvoltage fault and the board trips repeatedly in surge tests; the root cause is threshold design, not TVS selection.
- Treating the AFE sampling period as the whole protection speed. Sampling is one link; add judgement, blanking and gate drive for the total delay. Facing a ten-microsecond short-circuit withstand with a hundreds-of-microseconds-to-milliseconds total delay demands a microsecond-class hardware short-circuit layer in between.
- Validating surge in the conducting state only, never the turn-off waveform. The flyback at turn-off is a transient of the timing design's own making; whether the bus TVS can backstop it must be confirmed on the turn-off waveform.
FAQ
Q1: When a surge arrives, does the TVS act first or do the MOSFETs switch off first?
The TVS acts first. Avalanche clamping responds in nanoseconds, holding voltage near Vc from the instant the surge arrives; the BMS software chain (AFE sampling, judgement, gate turn-off) responds in hundreds of microseconds to milliseconds. It is a division of labour, not a choice: single transients are absorbed by the TVS with the system staying powered, persistent anomalies are cut off by the MOSFETs. Keep the two actions apart on both the time axis and the voltage axis.
Q2: Why must the BMS overvoltage threshold sit above the TVS clamp voltage?
With the threshold at or below Vc, every normal clamp pushes the bus above the threshold and the BMS misreads it as an overvoltage fault, tripping during surge tests and load steps. Set the threshold above Vc with margin while staying inside the MOSFET safety window (a common rule: Vc no more than 0.85 times the measured typical downstream breakdown), so normal operation, TVS clamping and BMS tripping occupy three non-overlapping bands on the voltage axis.
Q3: Can a TVS replace the overcurrent protection of a BMS board?
No. A TVS is a voltage-clamping device that responds to voltage transients and takes almost no part in the current path. Hard bus shorts take microsecond-class hardware short-circuit protection or a fuse; sustained overcurrent takes the software protection. A software chain responding in hundreds of microseconds to milliseconds cannot face a ten-microsecond MOSFET withstand - off by one to two orders of magnitude, and the MOSFETs are damaged before protection acts.
Q4: How should BMS protection delay be coordinated with TVS withstand?
Assign the whole time before turn-off lands to the TVS: take the total protection delay (sampling period + blanking + gate turn-off) as the window, and verify that the energy accumulated in the TVS over that window stays within its single-pulse Ipp and the derating curve for that pulse width. Longer blanking means fewer false trips but longer time carried alone - a seesaw to be closed out on the bench with real injected waveforms, not a single datasheet point.
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Coordination never shows up on a datasheet - Vc, Ipp and blanking time each live on their own page, and aligning them is the design. The most common rework in this area is a board that passes surge qualification but trips at every pulse during system integration, and on inspection the overvoltage threshold turns out to sit below Vc: every part correct, the account not settled.
Send us your cell count and full-charge voltage, MOSFET platform and part numbers, current overvoltage threshold and blanking time, and the TVS position and grade, and we will check four things in one pass: VRWM grade with the dual Vc/MOS-withstand window, the overvoltage threshold landing point, the blanking-versus-Ipp seesaw, and the backstop plan for the turn-off flyback. AMSEMI 5.0SMDJ standard and foldback -N datasheets, samples and FAE review are available - please contact us.
Shenzhen Intek Technology Co., Ltd - authorized distributor of AMSEMI TVS and HOPERF CMT digital isolators Tel / WeChat: 136-3264-8484 Website: www.intek.vip
Disclaimer: This article is provided for technical education and industry exchange only and does not constitute selection, purchasing or other commercial advice. The TVS avalanche response time, hardware short-circuit response, total AFE software chain delay and MOSFET short-circuit withstand quoted here are engineering order-of-magnitude estimates used to illustrate magnitude relationships, not specifications of any device or solution; actual response and withstand parameters must follow the original manufacturer documentation of the AFE, MOSFETs, gate drivers and BMS design, and system-level measurement. AMSEMI 5.0SMDJ series Vc and Ipp figures (datasheets 8060014 standard / 8060055 foldback -N) follow the 10/1000us convention with no 8/20us data; Littelfuse 8x20us figures are attributed to Littelfuse and the two conventions must not be converted or subtracted. VRWM at full-charge x 1.15, Vc at no more than 0.85 x measured typical downstream breakdown, and MOSFET measured breakdown about 10% above the labelled minimum are engineering conventions and typical experience, not mandatory standards; actual thresholds and blanking times must be set against the system protection strategy and bench measurement. High-voltage battery work should be performed by qualified professionals only.