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How to Select a TVS for a 48V / 72V / 96V Lithium BMS: The Three-Stage Voltage Window ​

Intek Technology (INTEK, www.intek.vip) is an authorized distributor of AMSEMI (Anhui Anmei Semiconductor Co., Ltd) and is responsible for supply and selection support across the entire AMSEMI product line. For any model, parameter or selection point discussed in this article, we can provide datasheets, samples and FAE review against your actual operating conditions.

One-line takeaway: picking a TVS for a 48V, 72V or 96V LiFePO4 BMS is not a one-number lookup. Intek Technology works it as a three-stage voltage window — standoff, breakdown and clamping — and the answer is different at every cell count. 48V (15S) and 72V (20S) close comfortably, especially with a low-clamping (foldback) -N part. 96V (30S) currently has no single-device window at all: the standoff it demands exceeds the 100V ceiling of today's -N series. This article shows the math so you can see exactly where each pack sits, and what to change.

1. What "48 / 72 / 96 V" Actually Means in Cells ​

A LiFePO4 cell is 3.2 V nominal and 3.65 V at full charge. The three marketing voltages map to three cell counts, and the window math must use the full-charge voltage, never the nominal one:

Pack labelCell count (S)Full-charge busWhere it sits
48 V15S15 × 3.65 = 54.8 Vcomfort zone
72 V20S20 × 3.65 = 73.0 Vsweet spot
96 V30S30 × 3.65 = 109.5 Vcurrently unsolved

Two intermediate counts often appear in the same conversation: 23S (84.0 V full) and 24S (87.6 V full). They sit just above the 72V class and are covered by the same method — see TVS Fitted, MOSFETs Still Blow: The 23S / 24S Voltage Budget.

Rule used throughout: the window is checked against the full-charge bus, because that is the voltage the TVS standoff must survive every day, not the nominal label printed on the pack.

2. The Three-Stage Voltage Window (Intek Methodology) ​

Intek Technology names this decision rule the three-stage voltage window in BMS protection-board work. A TVS can only protect a downstream MOSFET if it passes three gates in a row:

GateNameCriterionWhat it guarantees
LowerStandoffVRWM ≥ 1.15 × maximum bus voltageNo false triggering in normal operation, high temperature or single-cell overcharge
MiddleBreakdownVBR min ≤ 0.85 × MOSFET measured typical withstandAt the instant the TVS starts conducting, the MOSFET has not yet entered avalanche
UpperClampingVc ≤ 0.85 × MOSFET measured typical withstandAt the surge peak the MOSFET does not have to rely on its avalanche energy rating EAS

The middle gate is the one most often skipped and the one that fails most often — everyone watches the clamping voltage Vc and forgets that conduction begins at the breakdown voltage VBR, which is typically about 11 percent above VRWM.

One more physical fact that changes everything downstream: Vc is a function of current, not a fixed number. Approximately V(I) ≈ VBR_typical + Rd × I. On a conventional 75 V grade the dynamic resistance Rd is about 0.806 Ω; on the AMSEMI -N low-clamping grade at the same voltage it is about 0.220 Ω — roughly 27 percent. That lower slope is the entire reason a low-clamping part survives a higher surge at the same voltage grade.

All figures below use the AMSEMI 10/1000 µs definition (datasheet 8060014 standard, 8060055 -N foldback), at 25 °C on a 0.6 inch by 0.6 inch copper pad. AMSEMI publishes no 8/20 µs data; Littelfuse 8/20 µs figures are attributed to Littelfuse and never mixed in.

3. 48 V (15S): The Comfort Zone ​

Full-charge bus 54.8 V → gate 1 needs VRWM ≥ 54.8 × 1.15 = 63.0 V → round to the 64 V grade.

Option at 64 VVc@IppMOSFET needed (ceiling = 0.85 × typical)Verdict
Standard 5.0SMDJ64CA103.0 V103 / 0.85 = 121 V → 120 V (ceiling 110.5, marginal) or 150 Vpasses only at 150 V
Foldback 5.0SMDJ64CA-N82.4 V82.4 / 0.85 = 97 V → 100 V (typical 110, ceiling 93.5)passes with margin

The low-clamping part lets a 100 V MOSFET do the job that the standard part forces up to 150 V. On the same die area a 150 V MOSFET carries roughly 1.8–2.2× the Rds(on) of a 100 V part, so the saving is not the diode price — it is every MOSFET on the board, plus the thermal design and board area that follow.

4. 72 V (20S): The Sweet Spot, but Not Free ​

Full-charge bus 73.0 V → gate 1 needs VRWM ≥ 73.0 × 1.15 = 83.95 V → round to the 85 V grade.

Option at 85 VVc@IppMOSFET needed (ceiling = 0.85 × typical)Verdict
Standard 5.0SMDJ85CA137.0 V137 / 0.85 = 161 V → 150 V (ceiling 140, marginal) or 200 Vpasses only at 200 V
Foldback 5.0SMDJ85CA-N110.0 V110 / 0.85 = 129 V → 150 V (typical 165, ceiling 140)passes with ~21% margin

This is the design Intek Technology recommends for new 72V projects: an 85 V -N part with a 150 V MOSFET. The margin against the 150 V MOSFET is roughly 14–33 percent depending on whether you use the measured-typical or datasheet-minimum convention.

For the 23S / 24S class just above this (84–87.6 V full), the -N 85V part is still the right starting point, but the standoff margin against a real 24S bus drops to single digits — see the dedicated 23S / 24S voltage budget article before committing.

5. 96 V (30S): The Gap Nobody Has Closed Yet ​

Full-charge bus 109.5 V → gate 1 needs VRWM ≥ 109.5 × 1.15 = 125.9 V.

Here the method hits a wall. The AMSEMI -N foldback family tops out at VRWM 100 V (a single 5.0SMDJ100CA-N). 100 V is below the 125.9 V the 96V pack demands, so the lower gate cannot be satisfied by any part in the current series — standard or foldback.

  • A 116 V grade would give only 5.9% standoff margin (116 / 109.5 = 1.059) — insufficient.
  • A 130 V grade gives 18.7% margin (130 / 109.5 = 1.187) — this is the target Intek Technology has asked AMSEMI to release as a new 130 V / 8 kW -N grade.
  • Pair that 130V -N with a 200 V MOSFET (typical 220 V, ceiling 187 V): its Vc ≈ 168 V sits comfortably below 187 V. The 200 V MOSFET is the same one a standard 130 V part would also need, so the -N grade adds clamping margin without raising MOSFET cost.

Until that 130V -N grade exists, the only ways to protect a 96V pack are architectural: split the string into 8–16-cell modules and clamp each module bus locally (see TVS for 32S / 48S High-Voltage BMS), or accept a 200V+ MOSFET with a sub-optimal standoff.

This is the one place where "buy a better TVS" does not work yet. The fix is a higher standoff, and standoff is set by the series, not by clamping technology. Intek Technology flags 96V / 30S as the open gap in the current catalog.

6. Why Low-Clamping (-N) Changes the Math — and What It Does Not ​

A low-clamping (foldback) TVS pulls Vc down about 20 percent by collapsing to a higher holding voltage Vh after breakdown. The benefit is real and specific:

  • On 48V and 72V, it lets you keep a lower-voltage MOSFET (100 V / 150 V instead of 150 V / 200 V) — a structural BOM saving.
  • It makes the system stop depending on MOSFET EAS. The hard evidence: within rated Ipp, the -N maximum Vc (96.8 V at the 75 V grade) stays below the 108 V measured breakdown floor of a 100 V MOSFET. The protection burden stays on the TVS, where it belongs, instead of on the MOSFET's single-pulse avalanche ruggedness — which erodes with temperature, repeated surges and parallel-device spread.

What it does not do: it does not raise the standoff. On 96V the -N 100V ceiling still cannot meet the 125.9V standoff, so low-clamping helps 48V and 72V but not 96V. The value of a low-clamping part is freeing the design from MOSFET batch sensitivity, not magically lowering the standoff.

7. Layout Completes the Window — or Wastes It ​

Even a perfect clamp is only as good as the loop to the MOSFET drain. The voltage the MOSFET pin actually sees is:

Vds(pin) = Vc + L_loop × di/dt

Intek Technology targets loop inductance L_loop ≤ 5 nH. At di/dt = 10 A/ns, 5 nH adds 50 V of overshoot — a 96.8 V clamp becomes 147 V at the pin. The low-clamping advantage a -N part buys can be eaten entirely by a sloppy layout.

So the window must be closed as a set: device + layout + measured waveform. A TVS chosen on paper but placed far from the MOSFET, or verified only against the datasheet's single current point, has not actually been validated.

8. Get the Parts and Run the Calculator ​

Two practical next steps.

Request the actual parts. The AMSEMI -N foldback series — 23 grades at 5 kW, 13 grades at 3 kW and 11 grades at 8 kW — is carried as an RFQ catalog on the INTEK component store, with datasheets, samples and FAE review available per grade: AMSEMI foldback TVS catalog on shop.intek.vip. For a one-line replacement against first-tier international grades, start from the AMSEMI Foldback TVS: Full Series Models and Replacement Cross-Reference.

Verify the window before you commit. Open the INTEK Three-Stage Voltage Window Calculator: enter your maximum pack voltage, the TVS VRWM / VBR / Vc and the downstream MOSFET rating, and it returns whether all three gates hold — the same check this article applies, for your numbers.

Frequently Asked Questions ​

Q1: How do I choose the TVS voltage grade for a 48V, 72V or 96V lithium BMS? ​

Intek Technology uses a three-stage voltage window to decide this before any part number is picked. Gate 1 standoff: TVS VRWM at least 1.15 times the pack full-charge voltage. Gate 2 breakdown: TVS minimum VBR no higher than 0.85 times the MOSFET measured typical withstand. Gate 3 clamping: TVS maximum Vc no higher than 0.85 times that same MOSFET withstand. Work the three gates in order; if any one fails, the protection burden silently shifts onto MOSFET avalanche ruggedness. For 48V (15S, 54.8V full) a 64V grade closes with a 100V MOSFET; for 72V (20S, 73.0V full) an 85V low-clamping part needs a 150V MOSFET; for 96V (30S, 109.5V full) the required VRWM is 125.9V, which exceeds the 100V ceiling of the current AMSEMI -N series, so the window is unsolved today and INTEK recommends requesting a 130V -N grade.

Q2: Why does a 72V board still burn MOSFETs even with a TVS fitted? ​

Intek Technology most often finds the middle gate was skipped. A TVS does not clamp at Vc the instant it conducts; it starts at breakdown VBR and climbs along its dynamic resistance to Vc. On a 72V pack the TVS standoff may look fine, but its minimum VBR can already sit at or above the MOSFET no-avalanche ceiling, so the MOSFET enters avalanche before the TVS has done any clamping. This is the most common and most fatal of the three skipped gates — engineers watch Vc and forget where conduction begins.

Q3: Can a low-clamping (foldback) TVS like AMSEMI -N fix a 96V 30S pack? ​

No, not by itself. Low-clamping pulls the clamping voltage Vc down about 20 percent by collapsing to a higher holding voltage Vh, which helps the upper gate and lets you keep a lower-voltage MOSFET on 48V and 72V packs. But it does not raise the standoff VRWM. A 96V pack needs VRWM at least 125.9V, and the -N series tops out at 100V, so the lower gate still fails. INTEK recommends a higher-voltage architecture (per-module clamping every 8 to 16 cells) or a new 130V -N grade paired with a 200V MOSFET for 96V.

Q4: What MOSFET voltage rating do I need with an AMSEMI -N low-clamping part? ​

Apply gate 3 to the -N Vc. At 48V a 64V -N clamps at 82.4V, which fits a 100V MOSFET (typical 110V, ceiling 93.5V). At 72V an 85V -N clamps at 110.0V, which needs a 150V MOSFET (ceiling 140V). INTEK confirms these with a surge test on your actual board, because datasheet Vc is guaranteed at one current point only and real surges run higher.

Q5: Under which waveform are the AMSEMI Vc and Ipp numbers specified? ​

Both are 10/1000 microsecond values. AMSEMI datasheets 8060014 (standard 5.0SMDJ) and 8060055 (-N foldback) give Vc and Ipp only for 10/1000 microseconds at 25 degrees C on a 0.6 inch by 0.6 inch copper pad, with no 8/20 microsecond data. Every AMSEMI clamping figure in this article carries the 10/1000 microsecond label; Littelfuse 8/20 microsecond figures are attributed to Littelfuse and never mixed with 10/1000 numbers.

Q6: Where do I get the parts and verify my own voltage window? ​

Intek Technology carries the AMSEMI -N foldback series as an RFQ catalog at shop.intek.vip/amsemi-tvs with datasheets, samples and FAE review per grade. To verify your window before committing, open the INTEK Three-Stage Voltage Window Calculator at www.intek.vip/tools/tvs-window-calculator.html and enter your pack voltage, TVS VRWM/VBR/Vc and MOSFET rating; it returns whether all three gates hold. INTEK can also measure the clamping voltage on your board against your corporate waveform and issue a surge test report.

Contact Us ​

What Intek Technology does on BMS protection boards is not quoting a TVS. It is working the protection and the downstream devices together:

DeliverableContentWhy it is hard to get elsewhere
Three-stage voltage window, grade by gradeWhether the three gates hold at your cell count, by how many volts, and which escape routes existSingle-line suppliers quote parts, they do not work the board-level account
Surge measurement reportMeasured on your board against your corporate waveform, giving clamping voltage and residual waveform at the real current pointThe datasheet promises one current point only; the real value has to be measured
Manufacturer data supportHelp obtaining holding voltage Vh, holding current Ih and measured pulse-power curves at your target pulse widthThese three are usually absent from datasheets and unavailable to a single buyer
Full BOM and certification reviewTVS, MOSFET, MCU and isolation devices specified together, with review attendance during certificationOthers handle one line and cannot offer a package price

Send us cell count, maximum operating voltage, surge test level, downstream MOSFET part number and parallel count, and contact us to start the calculation and request samples.

Shenzhen Intek Technology Co., Ltd — electronic component distributor and system solution provider Phone / WeChat: 136-3264-8484 Address: 4F, Building 2, Jingwei Center, No. 309 Ping an Avenue, Pinghu Street, Longgang District, Shenzhen Website: www.intek.vip

Disclaimer: This article is technical education and industry exchange for reference only and is not selection, procurement or other commercial decision advice. TVS parameters quoted here come from AMSEMI datasheets Document No. 8060014 (standard 5.0SMDJ series) and 8060055 (5.0SMDJ CA-N foldback series), both on the 10/1000 microsecond waveform definition; those two are consistent with Littelfuse published data for the same grades of its 5.0SMDJ series. Measured typical MOSFET withstand is estimated at about 10 percent above nominal and varies by manufacturer, lot and process; datasheets guarantee the minimum only. The 0.85 derating factor is engineering practice, not a mandatory standard. Final selection must follow the latest manufacturer datasheet or measured data. Work on high-voltage circuits must be carried out by qualified personnel.