English

简体中文

English

简体中文

Appearance

Low-Clamp TVS for BMS MOSFET Protection: Why It Frees the System from EAS Sensitivity ​

Intek Technology (INTEK, www.intek.vip) is an authorized distributor of AMSEMI (Anhui Anmei Semiconductor Co., Ltd) and is responsible for supply and selection support across the entire AMSEMI product line, including the -N low-clamp / foldback TVS series. For any model, parameter or selection point discussed in this article, we can provide datasheets, samples and an FAE review against your actual operating conditions.

Bottom line: a low-clamping TVS is valuable not because it lets you drop the MOSFET voltage rating, but because it removes the system's dependence on the MOSFET's avalanche-energy (EAS) tolerance and batch sensitivity. On a BMS protection board the downstream MOSFET is the part that actually blows; a low-clamp part keeps it out of deep avalanche, so the whole design is no longer hostage to which MOSFET batch you happened to buy. This article explains the mechanism, the layout caveat that can erase the advantage, and how to prove it on your own board with a measured waveform.

1. The real question: what does "low clamping" actually change? ​

The usual pitch is "lower Vc → use a lower-voltage MOSFET → lower BOM." That framing is misleading and, taken alone, can push a designer into a corner (a lower-voltage MOSFET has its own tighter margin).

The mechanism that actually matters is different:

  • A conventional TVS follows the avalanche curve, so its clamping voltage keeps rising with surge current. At the high end of the Ipp range the residual voltage can exceed the MOSFET breakdown, forcing the MOSFET into avalanche.
  • An avalanche event is not a failure by itself — MOSFETs are avalanche-rugged. Destruction only happens when the avalanche energy exceeds the device EAS (single-pulse avalanche energy rating).
  • A low-clamping (foldback) TVS pulls Vc down by about 20% at the same voltage grade, so the MOSFET never reaches deep avalanche in the first place. The benefit is that selection no longer depends on the MOSFET's EAS headroom or on batch-to-batch variation of that EAS.

That is the point worth selling: low clamping = freedom from EAS sensitivity, not "a cheaper MOSFET."

2. Clamping voltage is a function of current — and the slope is the differentiator ​

A TVS is not a fixed-voltage clamp. Its terminal voltage under surge is roughly:

V(I) ≈ VBR_typ + Rd × I

where Rd is the dynamic resistance of the device in its conducting region. Two parts at the same VRWM can publish the same Vc at one Ipp point yet behave very differently as current climbs — because their Rd differs.

At the 54V grade (10/1000µs, 57.5 A), the published numbers tell the story:

ModelTypeVc@IppReading
5.0SMDJ54CAConventional87.1 Vhigh slope, Vc climbs fast with I
5.0SMDJ54CA-NFoldback (low-clamp)69.6 Vlow slope, Vc stays low as I climbs
TP5.0SMD54CA-FL (Littelfuse FlatSuppressX)Foldback68.5 Vsame low-clamp level

The -N foldback sits at the same low-clamping level as the Littelfuse FlatSuppressX at overlapping grades. The real differentiator is the slope (Rd), not just the headline "20% lower Vc": as the surge current rises toward Ipp, the conventional part's Vc climbs away from the MOSFET budget while the foldback part holds. INTEK does not publish an exact Rd for external quotation — verify the per-grade Vc@Ipp against the AMSEMI datasheet (Doc. 8060055) before committing a design.

3. Entering avalanche ≠ blowing — the EAS dependency ​

This is the most misunderstood step in BMS TVS selection, and it is where the "low-clamp" argument lives.

  • Vc > BVDSS of the MOSFET means the MOSFET enters avalanche. It does not mean it fails.
  • MOSFETs are specified as avalanche-rugged; avalanche is a recoverable operating event.
  • The failure condition is avalanche energy > EAS. For a small package such as TO-252, EAS is only on the order of tens of millijoules, and it derates with junction temperature.

So a board can run for years with a "75V TVS + 100V MOS" combination and never blow — because the TVS is doing most of the work (see next section), and the MOSFET only dips into shallow avalanche within its EAS budget. The mistake is to assume "Vc exceeded BVDSS, therefore the design is wrong." It is wrong only when the energy exceeds EAS.

The low-clamp TVS changes the probability of that breach: by holding Vc below the MOSFET breakdown in the first place, it removes the avalanche event entirely, so the design stops depending on how good (or how consistent) that particular MOSFET batch's EAS happens to be.

4. Parallel current sharing: why "75V TVS + 100V MOS" is robust, not a hack ​

When a surge arrives, the TVS and the MOSFET body diode / clamp path sit in parallel. They share current by their dynamic resistance:

  • TVS dynamic resistance in the conducting region: on the order of ~0.8 Ω.
  • MOSFET on-resistance (even a "low-Rds(on)" part): several Ω.

Because the TVS resistance is roughly an order of magnitude lower, it shunts the overwhelming majority (often 90%+) of the surge current; the MOSFET sees only a small fraction. This is exactly why the "75V TVS + 100V MOS" pairing has run stably in the field for years — it is a sound, robust solution, and should not be dismissed.

The field failure first suspect is therefore not the TVS grade. It is usually one of:

  1. a cheaper MOSFET swap with a lower EAS than the original (the part that actually blows);
  2. a layout-induced overshoot that the TVS cannot see (Section 5);
  3. a surge energy well beyond the rated Ipp that no single TVS in that package was meant to absorb.

5. Layout eats the advantage: Vds = Vc + L_loop × di/dt ​

A low-clamp TVS helps the device terminal. The MOSFET pin sees something else:

Vds(pin) = Vc(TVS) + L_loop × di/dt
  • L_loop is the stray inductance of the TVS-to-MOSFET loop (and the MOSFET package/lead inductance).
  • With a fast edge of di/dt = 10 A/ns and just L_loop = 5 nH, the pin overshoot is ~50 V on top of Vc.
  • A TVS clamping at 96.8 V can therefore show ~147 V at the MOSFET pin — and a 5 nH loop is easy to achieve with a tight layout, but a sloppy one is far worse.

The practical rule: target L_loop ≤ 5 nH by placing the TVS directly across the protected node, with a short, wide loop and a ground return right next to the TVS. Otherwise the low-clamp benefit is spent on the PCB, not on the MOSFET.

This is why the message must always be delivered as a set: device (low-clamp TVS) + layout (loop inductance) + measured waveform. Quoting a low Vc number alone, without the layout and without a scope capture, is how a good part gets blamed for a board problem it did not cause.

6. The strongest opener: sell a measurement, not an assertion ​

When a customer's board is burning MOSFETs, the least useful thing is a generic "use our lower-Vc TVS" claim. The most useful is a measured waveform:

  1. Put an oscilloscope on the MOSFET drain-to-source on the customer's actual board, under the actual surge waveform they see in the field.
  2. Capture the Vds peak at the pin.
  3. Compare that peak against the EAS rating of that specific MOSFET batch.

If the peak is inside EAS → the MOSFET is fine, look at layout / cheaper-swap. If the peak exceeds EAS → the low-clamp TVS is the right fix, and now it is proven by their waveform, not by a brochure. INTEK provides this on-board surge measurement report as a service, together with a full voltage-window review — these are the non-comparable hooks that sit behind the part number.

7. When a low-clamp TVS is the right call (design stage) ​

Use a low-clamp / foldback TVS when you are still in the design stage and can answer these:

  • Which gate did the last board fail? (standoff / breakdown / clamping) — the clamping gate is where low-clamp helps.
  • What is the maximum pack voltage, and what VRWM does the Three-Stage Voltage Window demand? (INTEK's named selection method: VRWM ≥ 1.15× max bus, VBR(min) ≤ 0.85× MOS rating, Vc ≤ 0.85× MOS rating.)
  • Is the MOSFET EAS the binding constraint, or is it the avalanche voltage? Low-clamp addresses the EAS dependency.
  • What is the loop inductance in the layout? If it is not controlled, fix the layout first.

For high-cell-count packs the window tightens: a 96V (30S LiFePO4, ~109.5V full-charge) bus needs VRWM ≥ ~125.9V, which is beyond the -N series' 100V top grade — the right answer there is a higher VRWM grade (INTEK can route a 130V -N / 8kW request to AMSEMI), not a lower-voltage MOSFET.

8. FAQ ​

Q1: Why does INTEK position low-clamping TVS as the first lever in BMS MOSFET protection? ​

INTEK's field work on BMS protection boards shows the dominant failure mode is not the TVS itself but the MOSFET being pushed into avalanche by a too-high residual voltage. A low-clamping (foldback) TVS such as the AMSEMI -N series lowers Vc by about 20% at the same voltage grade, which changes the downstream stress budget — not by letting you drop the MOSFET voltage rating, but by removing the system's dependence on the MOSFET's avalanche-energy (EAS) tolerance and batch sensitivity.

Q2: Does a lower clamping voltage let me use a lower-voltage MOSFET? ​

Not the way it is often framed. The real gain of a low-clamping TVS is that the downstream stage no longer relies on the MOSFET's EAS (avalanche energy rating) to survive the surge. Entering avalanche is recoverable; destruction only occurs when the avalanche energy exceeds EAS. By pulling Vc down, a foldback TVS keeps the MOSFET out of deep avalanche in the first place, so selection is no longer hostage to MOSFET batch variation.

Q3: If a TVS is already fitted, why do MOSFETs still burn? ​

Usually because the conventional TVS leaves too high a residual voltage at high surge current, pushing the MOSFET into avalanche, and the field failure first suspect is often a cheaper MOSFET swap (lower EAS) or layout-induced overshoot. The MOSFET pin voltage is Vds = Vc + L_loop × di/dt; with a 10 A/ns edge and 5 nH of loop inductance the pin sees about 50 V of overshoot on top of Vc — which can erase the low-clamp advantage in a single event.

Q4: How should I prove a low-clamp TVS is the right fix on my board? ​

By measuring, not asserting. Capture the MOSFET drain-to-source voltage peak with an oscilloscope on your actual board under the real surge waveform, then compare that peak against the EAS rating of the specific MOSFET batch. INTEK provides on-board surge measurement reports and a full voltage-window review so the choice is backed by your own waveform rather than a generic claim.

Further Reading ​

Contact Us ​

For datasheets, samples, or an on-board surge measurement review based on your pack voltage and surge level, contact us. Intek Technology is the AMSEMI authorized distributor and focuses on using low-clamp / foldback TVS to remove BMS protection boards from dependence on MOSFET EAS tolerance, and can also provide whole-package BOM and certification-review support.

Shenzhen Intek Technology Co., Ltd — electronic components distributor and system solutions provider Tel / WeChat: 136-3264-8484 Address: 4F, Building 2, Jingwei Center, No. 309 Pingan Avenue, Pinghu Street, Longgang District, Shenzhen, China Web: www.intek.vip

Disclaimer: This article is for technical exchange. The AMSEMI parameters listed come from its official datasheet (10/1000µs waveform definition, Doc. 8060055 for the -N series). Clamping voltage is current-dependent; per-grade Vc@Ipp and the dynamic-resistance behaviour must be verified against the manufacturer's official documentation. The current-sharing, EAS and layout-inductance relationships described are qualitative engineering principles; exact numbers depend on the specific MOSFET, surge waveform, layout and temperature, and must be confirmed by full-system measurement. This article does not constitute selection, purchasing or commercial advice.